Selection technique for preventing a source port from becoming a destination port in a multi-port bridge for a local area network

• US 6,301,256 B1
• Filed: 04/22/1998
• Issued: 10/09/2001
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Vasa, Suresh L.
• Primary Examiner(s): TON, DANG T
• Application Number:
  US09/064,676
• Time in Patent Office: 1,266 Days
• Field of Search: 370/401, 370/428, 370/402, 370/429, 370/403, 370/404, 370/268, 370/239, 370/330, 370/412, 370/392, 370/431, 370/419, 370/421, 370/423, 370/425, 370/389, 370/399, 370/229, 370/396, 370/398, 370/406, 370/408, 370/254, 370/256, 370/257, 709/227, 709/249, 709/250, 709/223, 709/242, 709/228, 709/239
• US Class Current: 370/401
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/135 by jamming the transmission media
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

A selection technique for filtering packets in a multi-port bridge for a local area network, thus, preventing a source port for a packet from becoming a destination port for the packet. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which one or ones of the plurality of ports are the appropriate destination ports for the packet. Each of the ports is assigned a respective one of the signal lines of the communication bus. A product of utilizing the look-up tables is referred to as a bit-map of the destination ports for the packet. The bit-map includes a logic level for each signal line assigned to a port wherein the logic level is indicative of whether the corresponding port is a destination port for the packet. The bit-map is placed on the communication bus which is monitored by each port. If the source port is designated as a destination port in the bit-map, this indicates that the source and destination nodes are on the same segment of the network (intra-segment communication). From the bit map, the source port also determines whether any other port is designated as a destination for the packet. If no other port is designated as a destination, the source port discards the incoming packet, thus filtering the packet. If, however, any other port is also designated as a destination for the packet, the source port continues receiving the packet for transmission by such other port.

Claims

1. A multi-port bridge for interconnecting a plurality of segments of a local area network, the multi-port bridge comprising:

a) a communication bus having a plurality of signal lines;

b) a plurality of ports coupled to the communication bus, each port for receiving data packets from a corresponding segment of the local area network and for transmitting data packets bridged by the multi-port bridge to the corresponding segment, wherein each signal line from among the plurality of signal lines is assigned to a respective port among the plurality of ports; and

c) a control circuit coupled to the communication bus, wherein the control circuit determines which of the plurality of ports are a destination for each packet based upon a destination address contained in the packet and wherein the control circuit notifies a source port for each packet whether the source port is also a destination for the packet by applying a selected logic level to the signal line of the source port and, if the source port is also a destination for the packet, the packet is not transmitted by the source port to its corresponding segment.

2. The multi-port bridge according to claim 1 wherein the control circuit notifies the source port whether it is a destination for the packet while the packet is still being received by the multi-port bridge.

3. The multi-port bridge according to claim 2 wherein if the source port is a destination for the packet, then the packet is discarded while the packet is still being received by the multi-port bridge.

4. The multi-port bridge according to claim 1 wherein the control circuit notifies the source port for the packet whether any port other than the source port is also a destination for the packet by applying a selected logic level to each signal line corresponding to each other port.

5. The multi-port bridge according to claim 4 wherein if the source port is an only destination for the packet, then the packet is discarded and, if the source port is one of a plurality of destinations for the packet or if the source port is not a destination for the packet, then the entire packet is received.

6. The multi-port bridge according to claim 5 wherein the packet is discarded while it is being received.

7. The multi-port bridge according to claim 5 wherein the entire packet is received by the source port transferring the entire packet to a memory device.

8. The multi-port bridge according to claim 7 wherein the entire packet is transferred to the memory device while it is being received.

9. A method of controlling flow of packets in a multi-port bridge having a plurality of ports interconnected to a memory device by a communication bus comprising a plurality of signal lines, wherein each port of the plurality of ports is associated with a respective signal line, and wherein the multi-port bridge functions to interconnect a plurality of segments of a local area network, the method comprising steps of:

a) receiving a packet having a destination address into a receive buffer in the source port, wherein the packet is received from a segment associated with the source port;

b) looking-up the destination address in a table for determining one or more destination ports for the packet;

c) forming a bit-map for the packet, wherein individual bits of the bit map are correlated to respective ports, a logic level of each bit reflecting a status of each the plurality of ports, the status indicating whether or not a port is designated as a destination port according to the destination address within the packet;

d) placing the bit-map on the communication bus such that respective logic levels applied to the plurality of signal lines within the bus conform to the respective logic levels of the bit map;

e) determining whether the source port is a destination for the packet; and

f) performing the step of preventing the source port from transmitting the packet to its corresponding segment if the source port is a destination for the packet.

10. The method according to claim 9 wherein the step of determining comprises steps of:

a. transferring the destination address to a control circuit; and

b. comparing the destination address to entries in a table.

11. The method according to claim 9 wherein the step of preventing comprises a step of discarding the packet is while the packet is still being received by the multi-port bridge.

12. The method according to claim 9 further comprising a step of transferring the packet to an assigned location in the memory device.

13. The method according to claim 12 further comprising a step of storing indicia of the assigned location in the one or more destination ports, other than the source port.

14. The method according to claim 13 further comprising a step of retrieving the packet from the location into at least one of the destination ports for the packet having the indicia stored.

15. The method according to claim 9 wherein if the source port is an only destination for the packet, then the packet is discarded and, if the source port is one of a plurality of destinations for the packet or if the source port is not a destination for the packet, then the entire packet is received.

16. The method according to claim 15 wherein the packet is discarded while it is being received.

17. The method according to claim 15 wherein the entire packet is received by the source port performing a step of transferring the entire packet to an assigned location in the memory device.

18. The method according to claim 17 wherein the step of transferring the entire packet to the assigned location is performed while the packet is being received.

19. The method according to claim 17 further comprising a step of storing indicia of the assigned location in the one or more destination ports, other than the source port.

20. The method according to claim 19 wherein the indica includes an identification assigned to the packet and an address in the memory device representative of the location.

21. The method according to claim 17 further comprising a step of retrieving the packet from the location into at least one of the destination ports for the packet having the indicia stored.

22. The method according to claim 21 further comprising a step of transmitting the packet while the packet is being retrieved from the location.

23. The method according to claim 21 further comprising a step of receiving the packet from the source port into at least one of the destination ports for the packet while the packet is being stored at the location.

24. The method according to claim 23 further comprising a step of retrieving the packet from the location into at least one of the destination ports for the packet after the packet has been stored at the location.

25. A method of controlling flow of packets in a multi-port bridge having a plurality of ports configured to communicate with a respective plurality of segments, the multiport bridge further comprising a communication bus comprising a plurality of signal lines, each of the plurality ports being assigned to a respective signal line from among the plurality of signal lines, the method comprising steps of:

a) receiving a destination address for a data packet in a source port;

b) determining a status of each of the plurality of ports, the status of a port corresponding to whether or not a port is designated as a destination port according to the destination address of the data packet;

c) forming a bit map correlating a plurality of discrete logic levels to the status of the respective plurality of ports;

d) placing the bit map on the communication bus; and

e) determining if the source port is a destination port.

26. The method according to claim 25 further comprising the step of notifying the source port of whether or not it is a destination port for the packet while the packet is still being received by the multi-port bridge.

27. The method according to claim 26 further comprising the step of preventing the data packet from being transmitted into the segment corresponding to the source port if the source port is a destination for the packet.

28. The method according to claim 26 further comprising the step of notifying the source port for the packet whether any port other than the source port is a destination for the packet.

29. The method according to claim 28 further comprising the step of terminating any further action relative to the data packet if the source port is an only destination for the packet.

30. The method according to claim 28 further comprising the step of receiving the entire packet if a port other than the source port is designated as a destination port.

31. The method according to claim 30 further comprising the steps:

a) receiving a first portion of the data packet into a receive buffer;

b) transferring the first portion of the data packet into memory device other than the receive buffer; and

c) receiving a second portion of the data packet into the receive buffer, wherein the step of receiving the second portion takes place subsequent to the step of transferring the first portion.

32. The method according to claim 25 wherein the step of determining comprises steps of:

a) transferring the destination address to a control circuit; and

b) comparing the destination address to entries in a table.