Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer

  • US 6,303,464 B1
  • Filed: 12/30/1996
  • Issued: 10/16/2001
  • Est. Priority Date: 12/30/1996
  • Status: Expired due to Term
First Claim
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1. A method for forming a reduced capacitance interconnect system on a substrate, the method comprising:

  • forming a first metal interconnect layer including a first set of interconnect lines on the substrate, each of the interconnect lines being separated from an adjacent interconnect line by a trench, the trenches ranging in aspect ratio to a highest aspect ratio, the first metal layer being formed to a predetermined level above the substrate; and

    alternately depositing and etching a dielectric layer on the first metal interconnect layer such that enclosed voids are formed in at least each of the trenches having an aspect ratio above a predetermined minimum aspect ratio, each of the enclosed voids having a void tip substantially level with the top of the metal layer, the enclosed voids in each of the trenches having the highest aspect ratio having a volume that is 15% or more of a volume of the corresponding trench.

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