Data carrier having rectifier and improved voltage limiter
First Claim
Patent Images
1. A data carrier processing system comprising:
- a receiver adapted to receive and to supply a carrier signal which has been amplitude-modulated in dependence on transmitted data, one or more rectifiers, operably coupled to the carrier signal, that are adapted to generate a d.c. supply voltage corresponding to the carrier signal, a voltage limiter adapted to limit the d.c. supply voltage to a first limit value, a demodulator, operably coupled to the carrier signal, that is adapted to supply a data signal representative of the transmitted data, and a processor adapted to process the data signal supplied by the demodulator, the processor having a power supply input that is arranged to receive the d.c. supply voltage, wherein;
the voltage limiter is adapted to limit the d.c. supply voltage to the first limit value with a delay to amplitude variations in the carrier signal, the voltage limiter is further adapted to limit the d.c. supply voltage to a second limit value without delay to amplitude variations in the carrier signal, and the second limit value is higher than the first limit value.
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Accused Products
Abstract
A data carrier processing system is provided for receiving an amplitude-modulated carrier signal. The system includes rectifiers and a voltage limiter that limits the d.c. supply voltage that is provided by the rectifiers. The voltage limiter provides a delayed response to amplitude variations in the carrier signal, so as to avoid adverse effects on the modulation of the carrier signal, while also providing an un-delayed response to excess amplitude values, so as to avoid excessive d.c. supply voltage for circuit elements of the data carrier system.
55 Citations
28 Claims
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1. A data carrier processing system comprising:
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a receiver adapted to receive and to supply a carrier signal which has been amplitude-modulated in dependence on transmitted data, one or more rectifiers, operably coupled to the carrier signal, that are adapted to generate a d.c. supply voltage corresponding to the carrier signal, a voltage limiter adapted to limit the d.c. supply voltage to a first limit value, a demodulator, operably coupled to the carrier signal, that is adapted to supply a data signal representative of the transmitted data, and a processor adapted to process the data signal supplied by the demodulator, the processor having a power supply input that is arranged to receive the d.c. supply voltage, wherein;
the voltage limiter is adapted to limit the d.c. supply voltage to the first limit value with a delay to amplitude variations in the carrier signal, the voltage limiter is further adapted to limit the d.c. supply voltage to a second limit value without delay to amplitude variations in the carrier signal, and the second limit value is higher than the first limit value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
a first control signal generator adapted to generate and to supply a first control signal corresponding to the carrier signal, and a delay device, operably coupled between the first control signal generator and the voltage limiter, that is configured to receive the first control signal and to provide therefrom a delayed first control signal, and wherein the voltage limiter responds with the delay to amplitude variations in the carrier signal in dependence on the delayed first control signal supplied by the delay device.
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3. A data carrier processing system as claimed in claim 2, wherein:
the voltage limiter includes a circuit element whose resistance is variable in dependence on the first control signal.
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4. A data carrier processing system as claimed in claim 3, wherein
the circuit element is formed by a FET. -
5. A data carrier processing system as claimed in claim 3, further including:
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a second control signal generator adapted to generate and to supply a second control signal corresponding to the carrier signal, and the resistance of the circuit element is also variable in dependence on the second control signal in order to limit the d.c. supply voltage to the second limit value.
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6. A data carrier as claimed in claim 5, wherein
the first control signal generator and the second control signal generator are arranged after the one or more rectifiers and are configured to generate the first and second control signals corresponding to a rectified carrier signal from the one or more rectifiers. -
7. A data carrier processing system as claimed in claim 6, further including
additional one or more rectifiers, operably coupled between the receiver and the circuit element, that are configured to also vary the resistance of the circuit element. -
8. A data carrier processing system as claimed in claim 6, wherein
the one or more rectifiers are formed by a single bridge rectifier. -
9. A data carrier processing system as claimed in claim 2, wherein
the voltage limiter includes a current sink stage whose sink current is variable in dependence on the fist control signal. -
10. A data carrier processing system as claimed in claim 9, wherein
the current sink stage is formed by a FET current mirror circuit. -
11. A data carrier processing system as claimed in claim 2, further including
a second control signal generator adapted to generate and to supply a second control signal corresponding to the carrier signal without delay to the voltage limiter. -
12. A data carrier processing system as claimed in claim 11, wherein
the voltage limiter includes a circuit element for limiting the d.c. supply voltage to the second limit value, and the second circuit element has a resistance that is variable in dependence on the second control signal. -
13. A data carrier processing system as claimed in claim 12, wherein
the circuit element is formed by a FET. -
14. A data carrier processing system as claimed in claim 1, wherein
the voltage limiter includes a zener diode for limiting the d.c. supply voltage to the second limit value.
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15. A circuit comprising:
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one or more rectifiers that are configured to receive a carrier signal which has been amplitude-modulated in dependence on transmitted data and arc adapted to generate a d.c. supply voltage corresponding to the carrier signal, a voltage limiter adapted to limit the d.c. supply voltage to a first limit value, a demodulator, operably coupled to the carrier signal that is adapted to supply a data signal representative of the transmitted data, and a processor adapted to process the data signal supplied by the demodulator, the processor having a power supply input, which power supply input is arranged to receive the d.c. supply voltage, wherein;
the voltage limiter is adapted to limit the d.c. supply voltage to the first limit value with a delay to amplitude variations in the carrier signal, the voltage limiter is adapted to limit the d.c. supply voltage to a second limit value without delay to amplitude variations in the carrier signal, and the second limit value is higher than the first limit value. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
a first control signal generator adapted to generate and to supply a first control signal corresponding to the carrier signal, and a delay device, operably coupled between the first control signal generator and the voltage limiter, that is configured to receive the first control signal and to provide therefrom a delayed first control signal, and the voltage limiter responds with the delay to amplitude variations in the carrier signal in dependence on the delayed first control signal.
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17. A circuit as claimed in claim 16, wherein
the voltage limiter includes a circuit element whose resistance is variable in dependence on the first control signal. -
18. A circuit as claimed in claim 17, wherein
the circuit element is formed by a FET. -
19. A circuit as claimed in claim 17, further including
a second control signal generator adapted to generate and to supply a second control signal corresponding to the carrier signal, and wherein the resistance of the circuit element is also variable in dependence on the second control signal. -
20. A circuit as claimed in claim 19, wherein
the first control signal generator and the second control signal generator are arranged after the one or more rectifiers and are configured to generate the first and second control signals corresponding to a rectified carrier signal from the one or more rectifiers. -
21. A circuit as claimed in claim 20, further including
a receiver that is adapted to receive and to supply the carrier signal, and additional one or more rectifiers, operably coupled between the receiver and the circuit element, that are configured to also vary the resistance of the circuit element. -
22. A circuit as claimed in claim 20, wherein
the one or more rectifiers are formed by a single bridge rectifier. -
23. A circuit as claimed in claim 16, wherein
the voltage limiter includes a current sink stage whose sink current is variable in dependence on the first control signal. -
24. A circuit as claimed in claim 23, wherein
the current sink stage is formed by a FET current mirror circuit. -
25. A circuit as claimed in claim 16, further including
a second control signal generator adapted to generate and to supply a second control signal corresponding to the carrier signal without delay to the voltage limiter. -
26. A circuit as claimed in claim 25, wherein
the voltage limiter includes a circuit element for limiting the d.c. supply voltage to the second limit value, and the circuit element has a resistance which is variable in dependence on the second control signal. -
27. A circuit as claimed in claim 26, wherein
the circuit element is formed by a FET. -
28. A circuit as claimed in claim 15, wherein
the voltage limiter includes a zener diode for limiting the d.c. supply voltage to the second limit value.
Specification