Method of manufacturing components and component thereof

• US 6,310,403 B1
• Filed: 08/31/2000
• Issued: 10/30/2001
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lin, Jong-Kai, Lindsey, Scott E., Guo, Yifan, Zhang, Chunsheng, Li, Li
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/652,620
• Time in Patent Office: 425 Days
• Field of Search: 257/780, 257/781, 257/777, 257/686, 257/778, 257/786, 257/747, 438/108, 438/109, 438/110, 438/613, 438/107
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16108 the bump connector not being orthogonal to the surface
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H05K 2201/068 : wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09427 : Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 2203/048 : Self-alignment during soldering; Terminals, pads or shape of solder adapted therefor
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of manufacturing components includes providing a substrate (110, 531, 631, 700) having a first coefficient of thermal expansion (CTE), having a first surface (111), and supporting a first plurality of interconnects located over the first surface in a first predetermined pattern. The method also includes providing another substrate (190) having a second CTE, having a second surface (195), and supporting a second plurality of interconnects located over the second surface in a second predetermined pattern. The method further includes assembling together the two substrates at a first temperature outside of a temperature range of approximately 25 to 30° C.

Claims

1. A method of manufacturing components comprising:

providing a first substrate having a first coefficient of thermal expansion (CTE), having a first surface, and supporting a first plurality of interconnects located over the first surface in a first predetermined pattern;

providing a second substrate having a second CTE, having a second surface, and supporting a second plurality of interconnects located over the second surface in a second predetermined pattern; and

assembling together the first and second substrates at a first temperature outside of a temperature range of approximately 25 to 30°

C.,

wherein;

the first and second pluralities of interconnects are aligned with each other at the first temperature and are substantially misaligned with each other at a second temperature of the temperature range.

2. The method of claim 1 wherein:

providing the first substrate further comprises;

providing the first predetermined pattern located only at a periphery of the first surface; and

providing the second substrate further comprises;

providing the second predetermined pattern located only at a periphery of the second surface.

3. The method of claim 1 wherein:

providing the first substrate further comprises;

providing a first grid pattern for the first predetermined pattern; and

providing the second substrate further comprises;

providing a second grid pattern for the second predetermined pattern.

4. The method of claim 1 further comprising:

dispensing an underfill material between the first and second substrates; and

curing the underfill material between the first and second substrates.

5. The method of claim 1 wherein:

assembling together the first and second substrates further comprises;

heating the first substrate;

electrically coupling together the first and second pluralities of interconnects; and

cooling the first substrate to the first temperature.

6. The method of claim 5 wherein:

assembling together the first and second substrates further comprises;

heating the second substrate; and

cooling the second substrate to the first temperature.

7. The method of claim 5 wherein:

assembling together the first and second substrates further comprises;

aligning together the first substrate and the second substrate before heating the first substrate.

8. The method of claim 5 wherein:

electrically coupling together the first and second pluralities of interconnects occurs after heating the first substrate and before cooling the first substrate.

9. The method of claim 1 wherein:

providing the first substrate further comprises;

providing a first additional plurality of interconnects located over the first surface and adjacent to the first plurality of interconnects.

10. The method of claim 9 wherein:

providing the second substrate further comprises;

providing a second additional plurality of interconnects located over the second surface and adjacent to the second plurality of interconnects.

11. The method of claim 10 wherein:

assembling together the first and second substrates further comprises;

misaligning the first additional plurality of interconnects and the second additional plurality of interconnects at the first temperature; and

the first and second additional pluralities of interconnects are aligned with each other at the second temperature.

12. The method of claim 1 wherein:

providing the first substrate further comprises;

providing the first substrate with a first plurality of dice, each die in the first plurality of dice having a portion of the first plurality of interconnects; and

providing the second substrate further comprises;

providing the second substrate with a second plurality of dice, each die in the second plurality of dice having a portion of the second plurality of interconnects.

13. The method of claim 12 further comprising:

singulating the dice of the first plurality of dice from the first substrate; and

singulating the dice of the second plurality of dice from the second substrate.

14. The method of claim 13 wherein:

singulating the dice of the first plurality of dice from the first substrate occurs after assembling together the first and second substrates; and

singulating the dice from the second plurality of dice from the second substrate occurs after assembling together the first and second substrates.

15. The method of claim 12 wherein:

providing the first substrate further comprises;

providing a location for each of the portions of the first plurality of interconnects to be compensated by portion.

16. The method of claim 12 wherein:

providing the second substrate further comprises;

providing a location for each of the portions of the second plurality of interconnects to be compensated by portion.

17. The method of claim 12 wherein:

providing the first substrate further comprises;

providing a location for each of the portions of the first plurality of interconnects to be compensated by portion and compensated individually within the portion.

18. The method of claim 12 wherein:

providing the second substrate further comprises;

providing a location for each of the portions of the second plurality of interconnects to be compensated by portion and compensated individually within the portion.

19. The method of claim 1 wherein:

providing the first substrate further comprises;

providing a location for each interconnect of the first plurality of interconnects to be compensated individually.

20. The method of claim 1 wherein:

providing the second substrate further comprises;

providing a location for each interconnect of the second plurality of interconnects to be compensated individually.

21. The method of claim 1 wherein:

providing the first substrate further comprises;

providing a location for different groups of the first plurality of interconnects to be compensated by group.

22. The method of claim 1 wherein:

providing the second substrate further comprises;

providing a location for different groups of the second plurality of interconnects to be compensated by group.

23. A method of manufacturing semiconductor components comprising:

manufacturing a plurality of semiconductor devices and a first plurality of interconnects supported by a semiconductor wafer having a first coefficient of thermal expansion (CTE), the first plurality of interconnects having a first predetermined pattern located over a first surface of the semiconductor wafer;

disposing a plurality of interconnect bumps adjacent to the first plurality of interconnects;

providing a capping substrate having a second CTE, a second surface, and a second plurality of interconnects located over the second surface in a second predetermined pattern;

assembling together the semiconductor wafer and the capping substrate at a first temperature greater than approximately 30°

C.;

dispensing an underfill material between the semiconductor wafer and the capping substrate after assembling together the semiconductor wafer and the capping substrate; and

curing the underfill material,

wherein;

the first and second pluralities of interconnects are aligned with each other at the first temperature and are substantially misaligned with each other at a second temperature less than or equal to approximately 30°

C.

24. The method of claim 23 wherein:

manufacturing the plurality of semiconductor devices and the first plurality of interconnects further comprises;

providing the first predetermined pattern from a first group of patterns consisting of a first peripheral pattern located only at a periphery of the first surface and a first grid pattern located across the first surface;

providing the capping substrate further comprises;

providing the second predetermined pattern from a second group of patterns consisting of a second peripheral pattern located only at a periphery of the second surface and a second grid pattern located across the second surface.

25. The method of claim 23 wherein:

disposing the plurality of interconnect bumps occurs before assembling together the semiconductor wafer and the capping substrate; and

assembling together the semiconductor wafer and the capping substrate further comprises;

aligning together the semiconductor wafer and the capping substrate;

heating the plurality of interconnect bumps above the first temperature;

electrically coupling together the plurality of interconnect bumps and the second plurality of interconnects after heating the semiconductor wafer and the capping substrate;

cooling the plurality of interconnect bumps to the first temperature after electrically coupling together the plurality of interconnect bumps and the second plurality of interconnects; and

solidifying the plurality of interconnect bumps at the first temperature.

26. The method of claim 23 wherein:

manufacturing the plurality of semiconductor devices and the first plurality of interconnects supported by the semiconductor wafer further comprises;

manufacturing a first additional plurality of interconnects supported by the semiconductor wafer, located over the first surface, and located adjacent to the first plurality of interconnects;

providing the capping substrate further comprises;

providing a second additional plurality of interconnects located over the second surface and adjacent to the second plurality of interconnects; and

assembling together the semiconductor wafer and the capping substrate further comprises;

substantially misaligning the first additional plurality of interconnects and the second additional plurality of interconnects at the first temperature; and

aligning together the first additional plurality of interconnects and the second additional plurality of interconnects at the second temperature.

27. The method of claim 23 wherein:

manufacturing the plurality of semiconductor devices and the first plurality of interconnects supported by the semiconductor wafer further comprises;

manufacturing a first plurality of dice in the semiconductor wafer, each die in the first plurality of dice having at least one of the plurality of semiconductor devices and a portion of the first plurality of interconnects;

providing the capping substrate further comprises;

providing the capping substrate with a second plurality of dice, each die in the second plurality of dice having a portion of the second plurality of interconnects; and

the method further comprises;

simultaneously singulating the dice of the first plurality of dice from the semiconductor wafer and the dice from the second plurality of dice from the capping substrate after assembling together the semiconductor wafer and the capping substrate.

28. A component comprising:

a first substrate having a first coefficient of thermal expansion (CTE), a first surface, and a first plurality of interconnects located over the first surface in a first predetermined pattern;

a second substrate having a second CTE, a second surface, and a second plurality of interconnects located over the second surface in a second predetermined pattern,; and

wherein;

the first and second pluralities of interconnects are aligned with each other at a first temperature outside of a temperature range of approximately 25 to 30°

C.; and

the first and second pluralities of interconnects are substantially misaligned with each other at a second temperature in the temperature range.

29. The component of claim 28 wherein:

the first predetermined pattern is located only at a periphery of the first surface; and

the second predetermined pattern is located only at a periphery of the second surface.

30. The component of claim 28 wherein:

the first predetermined pattern comprises a first grid pattern located across the first surface; and

the second predetermined pattern comprises a second grid pattern located across the second surface.

31. The component of claim 28 further comprising:

an underfill material between the first and second substrates.

32. The component of claim 28 further comprising:

a first additional plurality of interconnects located over the first surface and adjacent to the first plurality of interconnects; and

a second additional plurality of interconnects located over the second surface and adjacent to the second plurality of interconnects,

wherein;

the first additional plurality of interconnects and the second additional plurality of interconnects are substantially misaligned at the first temperature; and

the first additional plurality of interconnects and the second additional plurality of interconnects are aligned together at the second temperature.

33. The component of claim 28 wherein:

the first substrate further comprises;

a first plurality of dice, each die in the first plurality of dice having a portion of the first plurality of interconnects; and

the second substrate further comprises;

a second plurality of dice, each die in the second plurality of dice having a portion of the second plurality of interconnects.

34. The component of claim 33 wherein:

a location for each of the portions of the first plurality of interconnects is compensated by portion.

35. The component of claim 33 wherein:

a location for each of the portions of the second plurality of interconnects is compensated by portion.

36. The component of claim 33 wherein:

a location for each of the portions of the first plurality of interconnects is compensated by portion and compensated individually within the portion.

37. The component of claim 33 wherein:

a location for each of the portions of the second plurality of interconnects is compensated by portion and compensated individually within the portion.

38. The component of claim 28 wherein:

a location for each interconnect of the first plurality of interconnects is compensated individually.

39. The component of claim 28 wherein:

a location for each interconnect of the second plurality of interconnects is compensated individually.

40. The component of claim 28 wherein:

a location for different groups of the first plurality of interconnects is compensated by group.

41. The component of claim 28 wherein:

a location for each portion of the second plurality of interconnects is compensated by group.