Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media

DC
  • US 6,311,239 B1
  • Filed: 10/29/1998
  • Issued: 10/30/2001
  • Est. Priority Date: 10/29/1998
  • Status: Expired due to Term
First Claim
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1. A circuit comprising:

  • a first circuit comprising a packer circuit and an encoder/serializer circuit, wherein said first circuit is configured to receive a first series of data packets having a first bit-width and present a second series of data packets having a second bit-width in response to said first series of data packets; and

    a second circuit comprising a decoder/deserializer circuit and an unpacker circuit, wherein said second circuit is configured to present a third series of data packets having said first bit-width in response to said second series of data packets.

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