CMOS active pixel sensor using a pinned photo diode

• US 6,320,617 B1
• Filed: 10/31/1996
• Issued: 11/20/2001
• Est. Priority Date: 11/07/1995
• Status: Expired due to Term

• Current Assignee: California Institute of Technology, Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Eastman Kodak Company
• Inventors: Gee, Russell Clayton, Lee, Paul Poo-Kam, Fossum, Eric R., Lee, Teh-Hsuang
• Primary Examiner(s): TILLERY, RASHAWN N
• Assistant Examiner(s): Wilson, Jacqueline
• Application Number:
  US08/742,002
• Time in Patent Office: 1,846 Days
• Field of Search: 348/302, 348/304, 348/308, 257/79, 257/80, 257/82, 257/292, 257/293, 257/294, 257/291, 257/290
• US Class Current: 348/302
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming

Abstract

Circuit architecture of an x-y addressable image sensor, in particular to that of a Complementary Metal Oxide Semiconductor (CMOS) active pixel sensor (APS). A substrate having an area divided into a plurality of pixel areas arranged in a series of rows and columns, having at least one control area separate from the pixel areas; a pinned photodiode formed in at least one of the pixel areas of the substrate; a readout transistor integrated on the pixel area of the substrate and operatively coupled to the pinned photodiode through a transfer gate and a charge to voltage converter; a row selection circuit having at least one selection transistor integrated on the substrate in the area for selecting the pixel area; a column selection circuit for selecting a group of pixels, the selection circuit formed in one of the control areas separate from the pixel areas, the selection circuit further comprising a column readout circuit including a double delta sampling circuit formed from a process that is compatible with CMOS technology; and a reset mechanism for resetting the floating diffusion. The present invention further comprises the use of overlapping gates to reduce the overall size requirements.

Claims

1. An active pixel sensor comprising:

a substrate having an area divided into a plurality of pixel areas arranged in a series of rows and columns, having at least one control area separate from the pixel areas;

a pinned photodiode formed in at least one of the pixel areas of the substrate;

a readout transistor integrated on the pixel area of the substrate and operatively coupled to the pinned photodiode through a transfer gate and a charge to voltage conversion means;

at least one row selection circuit integrated on the substrate that is capable of selecting one row of the pixel areas, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further includes a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR(NOR) function output;

a column selection circuit capable of selecting a group of pixels formed within the substrate in one of the control areas separate from the pixel areas, the column selection circuit further comprising a column readout circuit allocated for each of the columns including a double delta sampling circuit formed from a process that is compatible with CMOS technology; and

a reset circuit.

2. The sensor of claim 1 wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid polysilicon levels 1 and 2 gates.

3. The sensor of claim 1 wherein the column selection circuit further comprises at least one column selection circuit implemented with at least one stacked capacitor comprising:

a MOS capacitor underneath a poly1-poly2 capacitor; and

a crowbar switch incorporated into the column selection circuit.

4. The sensor of claim 1 wherein the transfer gate off voltage level controls blooming levels.

5. The sensor of claim 1 wherein the transfer gate on voltage (V+TX) setting completes charge transfer of the pinned photodiode.

6. A sensor as in claim 4 wherein the reset level is controlled by a reset drain voltage control signal.

7. A sensor as in claim 1 wherein pixel overlaps the poly-2 reset signal line with the poly-2 row selection line to maximize the optical fill factor.

8. An active pixel sensor, comprising:

a substrate having a plurality of pixel areas arranged in rows and columns, and at least one control area such that the control area is associated with at least one pixel.

a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) functioon activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR (NOR) function output;

at least one pixel area comprising;

a) an optically active area including a printed photodiode, integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein; and

b) an optically inactive area, including at least one readout transistor integrated on the substrate in the pixel area and operatively coupled to the pinned photodiode through a transfer gate;

the readout transistor being formed of a formation process that is compatible with CMOS technology; and

a plurality of correlated double sampling units within the pixel selection circuitry allocated such that there is a correlated double sampling unit for each of the columns.

9. A sensor as in claim 8, wherein the pixel selection circuitry includes a plurality of transistors formed into a logical gate arrangement, the transistors having controlling gates overlapping other of the gates, the logical gates used for column addressing.

10. A sensor as in claim 8 wherein the transistors in the pixel area have at least one overlapping gate.

11. An active pixel sensor, comprising:

a substrate having an area, the area functionally divided to form a plurality of pixel areas arranged in rows and columns;

a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR (NOR) function output;

each of the pixel areas comprising;

a) a light information receiving element, integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming light therein; and

b) control electronics, including at least one readout transistor element integrated on the substrate in the pixel area;

the readout transistor element being formed of a formation process that is compatible with CMOS technology; and

pixel selection circuitry elements, including a plurality of transistors having controlling gates, wherein at least one of the elements including gates on the substrate overlapping another of the gates on the substrate; and

a correlated double unit allocated for each of the columns outside the pixel area.

12. An active sensor as in claim 11, wherein the pixel selection circuitry elements include a plurality of transistors in series, at least one of the gates of one of the transistors having a part which overlaps at least a part of another gate of another transistor.

13. An active sensor as in claim 11, wherein the pixel selection circuitry elements include a plurality of transistors in series, at least a first gate of a first of the transistors having a first part which overlaps at least a part of a second gate of a second transistor, and having a second part which overlaps at least a part of a third gate of a third transistor.

14. An active sensor as in claim 11, wherein the light information receiving element is a pinned photodiode.

15. An active sensor, comprising:

substrate;

at least one pixel area, formed in the substrate, and comprising;

a) a light information receiving element, integrated on the substrate and functioning to accumulate an indication of incoming photons therein; and

b) a control area, including at least one readout transistor element integrated on the substrate in the pixel area;

wherein at least a portion of the light information receiving element overlapping and covering at least a portion of the control area;

the light information receiving element formed of a formation process usually used for CCDs, and the readout transistor element being formed of a foundation process that is compatible with CMOS technology;

a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR (NOR) function output; and

a correlated double sampling unit allocated for each column.

16. An active sensor as in claim 15 wherein the control area further includes a signal line including a control signal thereon, and wherein the light information receiving element covers at least a portion of the signal line.

17. An active sensor as in claim 16 wherein the signal line is a reset line.

18. An active sensor as in claim 17, wherein at least one of the elements includes a gate on the substrate overlapping another of the gates on the substrate.

19. An active sensor as in claim 15 wherein the light information receiving element is a pinned photodiode.

20. An active sensor, comprising:

a substrate having an area, the area being functionally divided to form a plurality of pixel areas arranged in rows and columns, and at least one control area;

each of the pixel areas comprising;

a) a light information receiving element employing a pinned photodiode integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein; and

b) control electronics, including at least one readout transistor element integrated on the substrate in the pixel area, and at least one selection circuit, the selection circuit comprising a plurality of transistors located adjacent one another, and wherein the transistors having gates on the substrate, at least one of the gates on the substrate overlapping another of the gates on the substrate;

the readout transistor element being formed of a formation process that is compatible with CMOS technology;

pixel selection circuitry elements, in the control area including a plurality of transistors having controlling gates, wherein at least one of the elements including gates on the substrate overlapping another of the gates on the substrate, and a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR (NOR) function output; and

a correlated double sampling unit allocated for each of the columns.

21. A mixed technology active pixel sensor, comprising:

a substrate having an area, the area functionally divided to form a plurality of pixel areas arranged in rows and columns, and at least one control area separate from the pixel areas;

a photodiode element integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein;

at least one readout transistor integrated on the substrate in the pixel area;

at least one selection transistor, integrated on the substrate in the pixel area to operate in selecting the pixel;

the readout transistor, and the selection transistor being formed of a formation process that is compatible with CMOS technology;

a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;

a level shifting circuit having coupled to the OR (NOR) function output; and

a column readout circuit formed in the control area including a double delta sampling circuit formed for each of the columns from a process that is compatible with CMOS technology.

22. An active pixel sensor that provides correlated double sampling comprising:

a substrate having an area functionally divided to form a plurality of pixels in a series of columns and rows, and at least one control area outside the area;

a light information receiving element, integrated on the substrate in the pixel area functioning to accumulate an indication of incoming photons therein, coupled to a transfer gate having clocking means to adjust the voltage of the transfer gate; and

at least one readout transistor element integrated on the substrate in the pixel area, and at least one selection circuit, the selection circuit comprising a plurality of transistors located adjacent one another, a sensing node, a switch, selectively operating to connect the sensing node to the readout transistor element, and a reset switch, operating to connect the sensing node to a reset level;

a column readout circuit including a double delta sampling circuit formed from a process that is compatible with CMOS technology;

pixel selection circuitry elements, including a plurality of transistors having controlling gates and a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates; and

a level shifting circuit having coupled to the OR (NOR) function output.

23. The sensor of claim 22 further comprising at least a first and a second chip input supplying a non-reset voltage, and a reset voltage to the control electronics.

24. A sensor as in claim 23, wherein at least one of the elements including gates on the substrate overlapping another of the gates on the substrate.