PCB adapter for IC chip failure analysis

• US 6,323,670 B1
• Filed: 02/11/1999
• Issued: 11/27/2001
• Est. Priority Date: 02/11/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Chung
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): Deb, Anjan K
• Application Number:
  US09/247,975
• Time in Patent Office: 1,020 Days
• Field of Search: 324/765, 324/755, 324/500, 324/757, 439/73, 439/350
• US Class Current: 324/756.05
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

An arrangement that allows convenient and cost effective mounting of semiconductor die during the process of semiconductor failure analysis. The die that is analyzed can be biased and electrical stimuli and stimuli response signals can be provided to and extracted form the die. The arrangement of the present invention imposes no restriction on the type and size of die that can be analyzed and does not require equipment modification costs other than the cost of the subject mounting arrangement. The die to be analyzed is to be mounted with the die backside facing the die-mounting platform, an optional opening in the die-mounting platform allows backside analysis of the die. A method for complete, reliable and quick analysis of integrated circuit chips.

Claims

1. A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising:

a printed circuit board;

a location or position on top of said printed circuit board for mounting said semiconductor die that is to be analyzed, a die that is to be analyzed being mounted on the surface of a printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in a cut out provided in the printed circuit board;

a clamping arrangement for said printed circuit board;

an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus;

a means for distributing electrical signals from said clamping arrangement to said location of said die to be examined;

contact points between said clamping arrangement and said means for distributing electrical signals; and

a means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.

2. The failure analysis assembly of claim 1, said clamping arrangement comprising a wire assembly of a plurality of electrical wires for connecting said electrical stimuli or stimuli response apparatus with said contact points.

3. The failure analysis assembly of claim 2, said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

4. The failure analysis assembly of claim 2, said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

5. The failure analysis assembly of claim 2, said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

6. The failure analysis assembly of claim 2, said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires to the device to be analyzed for biasing and analyzing said die during said analysis.

7. The failure analysis assembly of claim 1, said contact points comprising a multiplicity of electrical contacting pads.

8. The failure analysis assembly of claim 1, said means for distributing electrical signals from said clamping arrangement to said location for mounting said die to be analyzed comprising a multiplicity of printed circuit board wires.

9. The failure analysis assembly of claim 8, said printed circuit board wires having electrical power or direct current supply carrying characteristics.

10. The failure analysis assembly of claim 8, said printed circuit board wires having electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

11. The failure analysis assembly of claim 8, said printed circuit board wires having a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

12. The failure analysis assembly of claim 1, said jumper wires having power or direct current carrying characteristics.

13. The failure analysis assembly of claim 1, said jumper wires having alternating current or high frequency carrying characteristics.

14. A chip failure analysis assembly for mounting and performing failure analysis of an integrated circuit die having a plurality of leads, said failure analysis assembly comprising:

a printed circuit board;

a location or position on top of said printed circuit board for mounting the semiconductor die that is to be analyzed;

an opening within said circuit board which is aligned with and directly below said location or position on top of said printed circuit board for mounting the semiconductor die to be analyzed for back side analysis of said die, a die that is to be analyzed being mounted on a surface of the printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die that is to be analyzed being mounted on a glass surface where the glass surface is inserted in the opening provided in the printed circuit board;

a clamping arrangement for said printed circuit board;

an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus;

a means for distributing electrical signals from said clamping arrangement to the die to be analyzed;

contact points between said clamping arrangement and said means for distributing electrical signals; and

a means for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed, said means comprising jumper wires.

15. The failure analysis assembly of claim 14, said clamping arrangement comprising a wire assembly of a plurality of electrical wires for establishing electrical analysis conditions for said die to be analyzed.

16. The failure analysis assembly of claim 15, said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

17. The failure analysis assembly of claim 15, said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

18. The failure analysis assembly of claim 15, said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

19. The failure analysis assembly of claim 15, said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires for the device to be analyzed for biasing and analyzing said die during said analysis.

20. The failure analysis assembly of claim 14, said contact points comprising a multiplicity of pads.

21. The failure analysis assembly of claim 14, said means for establishing electrical contact between said contact points and said location for mounting the die to be analyzed comprising a multiplicity of printed board wires.

22. The failure analysis assembly of claim 21, said multiplicity of printed board wires having electrical power or direct current supply carrying characteristics.

23. The failure analysis assembly of claim 21, said multiplicity of printed board wires having power or electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

24. The failure analysis assembly of claim 21, said multiplicity of printed board wires having a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

25. The failure analysis assembly of claim 14, said jumper wires having power or direct current carrying characteristics.

26. The failure analysis assembly of claim 14, said jumper wires having alternating current or high frequency carrying characteristics.

27. A method for performing semiconductor chip failure analysis, comprising:

providing a failure analysis assembly, said failure analysis assembly comprising a printed circuit board, further comprising a location or position on top of said printed circuit board for mounting said semiconductor die that is to be analyzed, further comprising a clamping arrangement for said printed circuit board, further comprising an electrical interface of said clamping arrangement with electrical power supplies or electrical stimulus or electrical response analysis apparatus, further comprising a means for distributing electrical signals from said clamping arrangement to said location of said die to be examined, further comprising contact points between said clamping arrangement and said means for distributing electrical signals and further comprising bond wires for establishing electrical connections between said means for distributing electrical signals and said die to be analyzed;

mounting a die that is to be analyzed on the surface of the printed circuit board with a backside of the die in a plane of the surface of the printed circuit board, the die being mounted on a glass surface, the glass surface being inserted in an opening provided in the printed circuit board;

providing electrical stimulus signals to said semiconductor chip; and

performing said semiconductor chip failure analysis.

28. The method of claim 27, said clamping arrangement comprising a wire assembly of a plurality of electrical wires for connecting said electrical stimuli or stimuli response apparatus with said contact points.

29. The method of claim 28, said electrical wire assembly providing power to said contact points for biasing said die during said analysis.

30. The method of claim 28, said electrical wire assembly providing electrical stimulus signals to said contact points for functionally activating said die during said analysis.

31. The method of claim 28, said electrical wire assembly providing electrical stimulus response wiring from said contact points to said electrical interface for functionally analyzing electrical response signals during said analysis of said die.

32. The method of claim 28, said electrical wire assembly providing a multiplicity of power, electrical stimuli and electrical stimuli response wires to the device to be analyzed for biasing and analyzing said die during said analysis.

33. The method of claim 27, said contact points comprising a multiplicity of electrical contacting pads.

34. The method of claim 27, said means for distributing electrical signals from said clamping arrangement to said location for mounting said die to be analyzed comprising a multiplicity of printed circuit board wires.

35. The method of claim 34, said printed circuit board wires comprising electrical power or direct current supply carrying characteristics.

36. The method of claim 34, said printed circuit board wires comprising electrical stimulus/response signal or high frequency electrical signal carrying characteristics.

37. The method of claim 34, said printed circuit board wires comprising a multiplicity of power or direct current supply and electrical stimulus/response or high frequency carrying characteristics.

38. The method of claim 27, said jumper wires having power or direct current carrying characteristics.

39. The method of claim 38, said jumper wires having alternating current or high frequency carrying characteristics.