Synchronous semiconductor memory device having improved operational frequency margin at data input/output

• US 6,324,118 B1
• Filed: 03/12/1999
• Issued: 11/27/2001
• Est. Priority Date: 06/17/1998
• Status: Expired due to Term

• Current Assignee: Vachellia LLC (Acacia Research Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/266,918
• Time in Patent Office: 991 Days
• Field of Search: 365/230.03, 365/233
• US Class Current: 365/233.12
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A synchronous semiconductor memory device includes a latch for temporarily storing data to be output to the outside, and a latch temporarily storing data input from the outside. The latches operate based on an internal clock when exchanging data with internal memory block, and operate based on a clock in phase with an external clock when exchanging data with the outside.

Claims

1. A synchronous semiconductor memory device, comprising:

an input/output terminal for inputting/outputting data;

an input/output circuit exchanging said data with said input/output terminal,

said input/output circuit including

a first data holding circuit holding first data, and

a second data holding circuit holding second data;

a data bus exchanging said data with said input/output circuit; and

an internal circuit performing an operation of reading/storing said data from/to said data bus.

2. The synchronous semiconductor memory device according to claim 1, further comprising:

a first clock generating circuit for outputting a first clock in synchronization with an external clock; and

a second clock generating circuit outputting a second clock having different frequency from said first clock;

wherein

said first data holding circuit takes in said first data in response to the first clock from the outside through said input/output terminal and outputs said first data to said internal circuit in response to the second clock;

said second data holding circuit takes in said second data in response to the first clock from the outside through said input/output terminal, and outputs said second data to said internal circuit in response to said second clock; and

said first and second data are externally applied to said input/output terminal at different time points.

3. The synchronous semiconductor memory device according to claim 2, wherein said first data and said second data are first and second data of a burst data sequence input in a burst operation;

said data bus includes

a first data bus corresponding to first address area of said internal circuit,

a second data bus corresponding to second address area of said internal circuit;

said input/output circuit further includes

a data taking circuit receiving said first and second data through said input/output terminal, applying said first data to said first data holding circuit, and applying said second data to said second data holding circuit, in response to said first clock, and

a write data output circuit reading said first and second data in a group from said first and second data holding circuits in response to said second clock, outputting said first data either to said first or second data bus corresponding to a write address data applied externally, and outputting said second data to the other one of said first and second data buses; and

said internal circuit includes

a memory block, including

the first address area receiving data from said first data bus, and

the second address area receiving data from said second data bus.

4. The synchronous semiconductor memory device according to claim 2, wherein

said input/output circuit further includes a third data holding circuit holding third data output from said internal circuit,

said third data holding circuit taking in said third data in response to a third clock from said internal circuit through said data bus and outputting said third data to said input/output terminal in response to a fourth clock having different frequency from said third dock, and

a fourth data holding circuit for holding fourth data output from said internal circuit,

said fourth data holding circuit taking in said fourth data in response to the third clock from said internal circuit through said data bus, and outputting said fourth data to said input/output terminal in response to said fourth clock;

and

said third data and said fourth data are output to said input/output terminal at different time points.

5. The synchronous semiconductor memory device according to claim 1, wherein

said internal circuit includes a memory block having a first address area and a second address area;

said data bus includes

a first data bus, and

a second data bus;

said first data holding circuit exchanges data with said first address area through said first data bus; and

said second data holding circuit exchanges data with said second address area through said second data bus.

6. The synchronous semiconductor memory device according to claim 1, wherein

said input/output circuit further includes

a selecting circuit receiving output from said first and second data holding circuits and selectively outputting either of the outputs to said input/output terminal;

and

said selecting circuit selects first data holding circuit in synchronization with a first edge of a clock signal and outputs said first data to said input/output terminal, and selects said second data holding circuit in synchronization with a second edge following said first edge and outputs said second data to said input/output terminal.