Synchronous semiconductor memory device having improved operational frequency margin at data input/output

  • US 6,324,118 B1
  • Filed: 03/12/1999
  • Issued: 11/27/2001
  • Est. Priority Date: 06/17/1998
  • Status: Expired due to Term
First Claim
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1. A synchronous semiconductor memory device, comprising:

  • an input/output terminal for inputting/outputting data;

    an input/output circuit exchanging said data with said input/output terminal, said input/output circuit including a first data holding circuit holding first data, and a second data holding circuit holding second data;

    a data bus exchanging said data with said input/output circuit; and

    an internal circuit performing an operation of reading/storing said data from/to said data bus.

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