CMOS imager with selectively silicided gates

• US 6,333,205 B1
• Filed: 08/16/1999
• Issued: 12/25/2001
• Est. Priority Date: 08/16/1999
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/374,990
• Time in Patent Office: 862 Days
• Field of Search: 438/592, 438/655, 438/656, 438/200, 438/69
• US Class Current: 438/69
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Claims

1. A method of forming a CMOS imager, comprising the steps of:

forming an insulating layer over a semiconductor substrate having a photo-collection region;

forming at least one transistor gate over a portion of said insulating layer;

forming an opaque conductive layer over said photo-collection region, said at least one transistor gate and said insulating layer; and

selectively removing said opaque conductive layer from said insulating layer and said photo-collection region.

2. The method according to claim 1, wherein said photo-collection region includes a photogate.

3. The method according to claim 1, wherein said transistor gate includes a reset gate.

4. The method according to claim 3, further comprising a transfer gate.

5. The method according to claim 4, further comprising a row select gate.

6. The method according to claim 4, wherein said transfer gate and said reset gate are formed by depositing a doped polysilicon and selectively removing portions of said doped polysilicon to form transistor gates.

7. The method according to claim 6, wherein said doped polysilicon is selectively removed by etching.

8. The method according to claim 1, wherein said transistor gate includes an amplifying transistor.

9. The method according to claim 8, wherein said amplifying transistor is a source follower transistor.

10. The method according to claim 1, wherein said insulating layer is a silicon dioxide.

11. The method according to claim 10, wherein said insulating layer is deposited by thermal oxidation of silicon.

12. The method according to claim 1, wherein said opaque conductive layer is formed by depositing an opaque conductive silicide layer.

13. The method according to claim 12, wherein said opaque conductive silicide layer is a tungsten silicide.

14. The method according to claim 12, wherein said opaque conductive silicide layer is a titanium silicide.

15. The method according to claim 12, wherein said opaque conductive silicide layer is a cobalt silicide.

16. The method according to claim 12, wherein said opaque conductive silicide layer is a molybdenum silicide.

17. The method according to claim 12, wherein said opaque conductive layer silicide layer is deposited by chemical vapor deposition.

18. The method according to claim 12, wherein said opaque conductive layer silicide layer is deposited by sputtering.

19. The method according to claim 1, wherein said opaque conductive layer is formed by depositing an opaque conductive barrier metal layer.

20. The method according to claim 19, wherein said opaque conductive barrier metal layer is a TiN/W layer.

21. The method according to claim 19, wherein said opaque conductive barrier metal layer is a WN_x/W layer.

22. The method according to claim 19, wherein said opaque conductive barrier metal layer is a WN_x layer.

23. The method according to claim 19, wherein said opaque conductive barrier layer is deposited by chemical vapor deposition.

24. The method according to claim 19, wherein said opaque conductive barrier layer is deposited by sputtering.

25. The method according to claim 1, wherein said opaque conductive layer is selectively removed by etching.

26. The method according to claim 1, wherein a ring portion of opaque conductive layer remains over an outer periphery of said photo-collection region.

27. The method according to claim 26, further including adding a light shield over a portion of said imager.

28. A method of forming a CMOS imager, comprising the steps of:

forming an insulating layer over a semiconductor substrate having a doped photocollection region;

depositing a doped polysilicon layer over said insulating layer;

depositing a photocollection insulator over said photocollection region;

forming an opaque conductive layer over said doped polysilicon layer; and

patterning said imager to form at least one gate stack having said opaque conductive layer over said gate stack.

29. The method according to claim 28, wherein said photo-collection region includes a photogate.

30. The method according to claim 28, wherein said transistor gate stacks include a reset gate.

31. The method according to claim 30, further comprising a transfer gate stack.

32. The method according to claim 31, further comprising a row select gate stack.

33. The method according to claim 31, wherein said transfer gate and said reset gate are formed by depositing a mask and resist and selectively removing a portion of said opaque conductive layer, said doped polysilicon layer to form transistor gates.

34. The method according to claim 33, wherein said layers are selectively removed by etching.

35. The method according to claim 28, wherein said transistor gates include an amplifying transistor gate stack.

36. The method according to claim 35, wherein said amplifying transistor is a source follower transistor gate stack.

37. The method according to claim 28, wherein said insulating layer is a silicon dioxide.

38. The method according to claim 37, wherein said insulating layer is deposited by thermal oxidation of silicon.

39. The method according to claim 28, wherein said opaque conductive layer is formed by depositing an opaque conductive silicide layer.

40. The method according to claim 39, wherein said opaque conductive silicide layer is a tungsten silicide.

41. The method according to claim 39, wherein said opaque conductive silicide layer is a titanium silicide.

42. The method according to claim 39, wherein said opaque conductive silicide layer is a cobalt silicide.

43. The method according to claim 39, wherein said opaque conductive silicide layer is a molybdenum silicide.

44. The method according to claim 39, wherein said opaque conductive layer silicide layer is deposited by chemical vapor deposition.

45. The method according to claim 39, wherein said opaque conductive layer silicide layer is deposited by sputtering.

46. The method according to claim 28, wherein said opaque conductive layer is formed by depositing an opaque conductive barrier metal layer.

47. The method according to claim 46, wherein said opaque conductive barrier metal layer is a TiN/W layer.

48. The method according to claim 46, wherein said opaque conductive barrier metal layer is a WN_x/W layer.

49. The method according to claim 46, wherein said opaque conductive barrier metal layer is a WN_x layer.

50. The method according to claim 46, wherein said opaque conductive barrier layer is deposited by chemical vapor deposition.

51. The method according to claim 46, wherein said opaque conductive barrier layer is deposited by sputtering.

52. The method according to claim 44, wherein said silicide is selectively removed by etching.

53. The method according to claim 28, wherein a ring portion of opaque conductive layer remains over an outer periphery of said photo-collection region.

54. The method according to claim 53, further including adding a light shield over a portion of said imager.