Satellite payload processing system for switching uplink signals to time division multiplexed downlink signals

• US 6,333,922 B1
• Filed: 02/16/1999
• Issued: 12/25/2001
• Est. Priority Date: 11/05/1996
• Status: Expired due to Fees

• Current Assignee: WorldSpace, Inc.
• Original Assignee: WorldSpace, Inc.
• Inventors: Campanella, S. Joseph
• Primary Examiner(s): YAO, KWANG BIN
• Application Number:
  US09/250,263
• Time in Patent Office: 1,043 Days
• Field of Search: 370/316, 370/319, 370/320, 370/321, 370/323, 370/324, 370/325, 370/326, 370/465, 370/466, 370/470, 370/471, 370/474, 370/476, 370/478, 370/337, 370/343, 370/344, 370/345, 370/347, 370/348, 370/349, 370/412, 370/428, 370/429
• US Class Current: 370/319
• CPC Class Codes: H04B 7/18515 Transmission equipment in satellites or space-based relays
• CPC Class Codes: H04B 7/2043 Mixed mode, TDM and FDM systems

Abstract

An apparatus for switching symbols in parallel broadcast channels to time division multiplexed data streams comprises first and second ping-pong buffers. The first ping-pong buffer is configured to store a first plurality of the parallel broadcast channels therein. The second ping-pong buffer is operable to store a second plurality of the broadcast channels therein. The second plurality of broadcast channels arrive at the second ping-pong buffer prior to the arrival of the first plurality of broadcast channels at the first ping pong buffer. The apparatus also comprises a routing switch connected to the outputs of the first and second ping-pong buffers, and a first frame assembler connected to the routing switch. The routing switch controls the writing of the contents of the second ping-pong buffer to the first frame assembler.

Claims

1. Apparatus for switching symbols in parallel broadcast channels transmitted as respective frequency division multiple access carriers to time division multiplexed data streams comprising:

first and second ping-pong buffers, said first ping-pong buffer being configured to store a first plurality of said symbols in said parallel broadcast channels therein, said second ping-pong buffer being operable to store a second plurality of said symbols in said parallel broadcast channels therein, said second plurality of said symbols in said parallel broadcast channels having arrived at said second ping-pong buffer prior to the arrival of said first plurality of said symbols in said parallel broadcast channels at said first ping-pong buffer;

a routing switch connected to the outputs of said first and second ping-pong buffers; and

a first frame assembler connected to said routing switch, said routing switch being operable to control the writing of the contents of said second ping-pong buffer to said first frame assembler.

2. An apparatus as claimed in claim 1, further comprising a second frame assembler connected to said routing switch, said routing switch being operable to control the writing of the contents of said second ping-pong buffer to at least one of said first frame assembler and said second frame assembler.

3. An apparatus as claimed in claim 2, wherein said routing switch is operable control the writing of the contents of said second ping-pong buffer to both of said first frame assembler and said second frame assembler to generate two parallel time division multiplexed data streams.

4. An apparatus as claimed in claim 2, wherein said second frame assembler stores at least one framing bit to identify said symbols stored therein as a frame.

5. An apparatus as claimed in claim 4, wherein said frame comprises time slots and said second frame assembler stores at least one bit representing a time slot control channel to indicate in which of said time slots said symbols corresponding to respective ones of said parallel broadcast channels are stored.

6. An apparatus as claimed in claim 1, wherein said second ping-pong buffer is operable to store a third plurality of said broadcast channels, said routing switch being operable to control the writing of the contents of said first ping-pong buffer to said first frame assembler.

7. An apparatus as claimed in claim 1, wherein said first ping-pong buffer is operable to switch as few as a single one of said first plurality of said symbols therein at one time.

8. An apparatus as claimed in claim 1, wherein said second ping-pong buffer is operable to switch as few as a single one of said second plurality of said symbols therein at one time.

9. An apparatus as claimed in claim 1, wherein said first frame assembler is operable to insert at least one framing bit in said second ping-pong buffer to identify said symbols stored in said second ping-pong buffer as a frame.

10. An apparatus as claimed in claim 9, wherein said frame comprises time slots and said first frame assembler is operable to insert at least one bit representing a time slot control channel in said second ping-pong buffer to indicate in which of said time slots said symbols corresponding to respective ones of said parallel broadcast channels are stored.

11. An apparatus as claimed in claim 1, wherein said apparatus is on-board a satellite and said routing switch is controllable via control signals generated by a ground station and transmitted to said satellite.

12. A method of switching symbols in parallel broadcast channels to time division multiplexed data streams comprising the steps of:

receiving said parallel broadcast channels transmitted via frequency division multiple access carriers;

storing a symbol from each of said parallel broadcast channels into a routing buffer;

receiving a control signal designating to which of a plurality of frame assembler buffers said symbols in said routing buffer are to be written, said time division multiplexed data streams comprising frames, the duration of a frame corresponding to a symbol epoch; and

writing the contents of said routing buffer to at least one of said plurality of frame assembler buffers once symbol epoch in accordance with said control signal.

13. A method as claimed in claim 12, wherein said storing step comprises the step of:

storing a first plurality of symbols from respective ones of said parallel broadcast channels in a first memory location of said routing buffer;

storing a second plurality of symbols from respective ones of said parallel broadcast channels in a second memory location of said routing buffer, said second plurality of symbols having arrived at said second memory location prior to the arrival of said first plurality of symbols at said first memory location.

14. A method as claimed in claim 13, wherein said writing step comprises the step of writing said second plurality of symbols to at least one of said plurality of frame assembler buffers while said first plurality of symbols are being stored in said first memory location of said routing buffer.