Semiconductor memory device and method for reading data

• US 6,337,810 B1
• Filed: 10/12/2000
• Issued: 01/08/2002
• Est. Priority Date: 10/18/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Yamasaki, Kazuyuki, Egawa, Tonomi
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/688,324
• Time in Patent Office: 453 Days
• Field of Search: 365/189.05, 365/236, 365/230.06, 365/205
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS₀˜YS₃₁ input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD₀˜signal YD₁₂₇ from the Y selector. A latch circuit 7 latches a data signal DT₀˜data signal DT₁₂₇ from the sense amplifier circuit 8 into a first latch group and a second latch group via latch signals SAL0 and SAL1 respectively.

Claims

1. A semiconductor memory device comprising:

a memory cell array with a plurality of arranged memory cells which are selected by a column address and a row address;

a bit line selection circuit for selecting based on said column address a group comprising a predetermined number of bit lines, from bit lines connected with said plurality of memory cells selected by said row address;

a sense amplifier section comprised of sense amplifiers for determining data for each bit line output signals from memory cells input through said plurality of bit lines of said selected group, and outputting data from each of said bit lines as an determination result,

a first latch group and a second latch group connected in common to said sense amplifier section, for storing said data of each bit line output from said sense amplifier section, and

a latch selection circuit for selecting which of said first latch group data and said second latch group data to output, and then outputting a selection result as read data,

wherein during burst read operation, in cases where data of said first latch group is being output as read data, said second latch group stores data from said sense amplifier, and in cases where data of said second latch group is being output as read data, said first latch group stores data from said sense amplifier.

2. A semiconductor memory device according to claim 1, wherein said first latch group and said second latch group latch continuous data during a latency period.

3. A semiconductor memory device according to claim 1 further equipped with a sense amplifier control device, wherein when data is being stored from said sense amplifier into either one of said first latch group and said second latch group, said sense amplifier is set to an active state, and when data has been stored in either one of said first latch group and said second latch group, said sense amplifier is set to a non-active state.

4. A semiconductor memory device according to claim 1, further comprising a detection signal generation circuit for detecting, during latching of continuous data to said first latch group and said second latch group during a latency period, when latching of data from both said first latch group and said second latch group has been completed, and outputting a detection signal.

5. A semiconductor memory device according to claim 1, further comprising a counter for setting an input address as an initial value for a burst read column address, and counting from said set initial value each time a read signal is input, and generating a burst address.

6. A semiconductor memory device according to claim 5, wherein said counter comprises a first counter for generating a burst address for selecting which of said read data output from said first latch and said second latch will be output from an output terminal, and a second counter for generating a burst address which functions as a selection signal for selecting, from bit lines connected to said selected memory cell, bit lines of said group for connection to a sense amplifier.

7. A semiconductor memory device according to claim 5, wherein said counter comprises a first counter for generating a burst address for selecting which of said read data output from said first latch and said second latch will be output from an output terminal, a second counter for generating a burst address which functions as a selection signal for selecting from bit lines connected to said selected memory cell, bit lines of said group for connection to a sense amplifier, and a third counter for generating a burst address which functions as a column address.

8. A method of reading data from a semiconductor memory device comprising:

a first step for selecting, from a memory array with a plurality of arranged memory cells which are selected by a column address and a row address, a plurality of said memory cells based on said row address,

a second step in which a bit line selection circuit selects a group comprising a predetermined number of bit lines, based on said column address, from bit lines connected with selected said plurality of memory cells,

a third step in which a sense amplifier section determines output signals from memory cells, input via said plurality of bit lines of said selected group, using a sense amplifier corresponding with each bit line, and outputs data from each of said bit lines as an evaluation result,

a fourth step in which either one of a first latch and a second latch connected in common to said sense amplifier section stores said data of each bit line output from said sense amplifier section, and

a fifth step in which a latch selection circuit selects which of said first latch data and said second latch data to output, and then outputs selected latch data as read data,

wherein during burst read operation, in cases where data of said first latch is being output as read data, said second latch stores data from said sense amplifier, and in cases where data of said second latch is being output as read data, said first latch stores data from said sense amplifier.

9. A method of reading data from a semiconductor memory device according to claim 8, wherein said first latch group and said second latch group latch continuous data during a latency period.

10. A method of reading data from a semiconductor memory device according to claim 8, further comprising a sense amplifier control device, wherein when data is being stored from said sense amplifier into either one of said first latch group and said second latch group, said sense amplifier is set to an active state, and when data has been stored in either one of said first latch group and said second latch group, said sense amplifier is set to a non-active state.

11. A method of reading data from a semiconductor memory device according to claim 8, further comprising a detection signal generation circuit for detecting, during latching of continuous data to said first latch group and said second latch group during a latency period, when latching of data from both said first latch group and said second latch group has been completed, and outputting a detection signal.