Adaptive parallel processing analog and digital converter

• US 6,339,390 B1
• Filed: 06/20/2001
• Issued: 01/15/2002
• Est. Priority Date: 10/04/2000
• Status: Expired due to Term

• Current Assignee: Linearity LLC
• Original Assignee: Richard J. Velazquez, Scott R. Velazquez
• Inventors: Velazquez, Richard J., Velazquez, Scott R.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US09/885,584
• Time in Patent Office: 209 Days
• Field of Search: 341/118, 341/120, 341/141, 341/144, 341/155
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1009 Calibration
• CPC Class Codes: H03M 1/121 Interleaved, i.e. using multiple converters or converter parts for one channel

Abstract

In one aspect, the present invention is directed to a converter for converting a signal from a first format to a second format. The converter includes a decomposition section, a converter array operatively coupled to the decomposition section, and a recombination section operatively coupled to the converter array. The decomposition section includes an input to receive the input signal, a splitter to divide the input signal into a plurality of signals, a plurality of signal outputs, each of which provides as an output one of the plurality of signals, and a clock circuit having a plurality of clock outputs for providing sample clocks to the converter array. The converter array includes a plurality of converters each having a signal input to receive one of the plurality of signals, each having a clock input to receive one of the sample clocks and each having an output that provides a converted signal. At least one of the decomposition section and the recombination section includes filters for filtering one of the plurality of signals and the plurality of converted signals. Other aspects of the invention are directed to methods for adaptively calibrating analog and digital converters.

Claims

1. A method for adaptively calibrating a converter system that converts an input signal from a first format to a second format, the converter system including an analog processing section, a digital processing section, a clock skew circuit for providing a plurality of clock signals, and a plurality of converters to receive the plurality of clock signals and operatively coupled between the analog processing section and the digital processing section, the method for calibrating comprising steps of:

setting the delay of the converter system, and selecting a frequency response of the digital processing section to provide an accurate representation of the input signal;

wherein the step of selecting a frequency response is based upon actual measurements of the analog signal processing section.

2. The method of claim 1, wherein the step of setting a frequency response based upon actual measurements includes a step of adaptively measuring the phase or gain of the analog signal processing section.

3. The method of claim 1, wherein the step of setting a frequency response based upon actual measurements includes a step of adaptively measuring the analog signal processing section without interrupting the normal conversion operation of the converter system.

4. The method of claim 1 further comprising a step of setting a time skew between each of the plurality of clock signals based upon actual measurements of the analog signal processing section.

5. A method for adaptively calibrating a converter system that converts an input signal from a first format to a second format, the converter system including an analog processing section, a digital processing section, a clock skew circuit for providing a plurality of clock signals, and a plurality of converters to receive the plurality of clock signals and operatively coupled between the analog processing section and the digital processing section, the method for calibrating comprising steps of:

setting the delay of the converter system, and

selecting a frequency response of the digital processing section to provide an accurate representation of the input signal;

wherein the step of setting the system delay is based upon actual measurements of the analog signal processing section.

6. A converter for converting an input signal from a first format to a second format, the converter comprising:

a decomposition section;

a converter array operatively coupled to the decomposition section; and

a recombination section operatively coupled to the converter array;

wherein the decomposition section includes;

an input to receive the input signal;

a splitter to divide the input signal into a plurality of signals;

a plurality of signal outputs, each of which provides as an output one of the plurality of signals; and

a clock circuit having a plurality of clock outputs for providing sample clocks with non-uniform sample period to the converter array;

wherein the converter array includes a plurality of converters, each of the converters having a signal input to receive one of the plurality of signals, a clock input to receive one of the sample clocks and an output that provides a converted signal; and

wherein at least one of the decomposition section and the recombination section includes filters for filtering either the plurality of signals or the plurality of converted signals.

7. The converter of claim 6, wherein the first format is digital, the second format is analog, and each of the converters of the converter array is a digital to analog converter operating on non-uniform channel bandwidths.

8. A converter for converting an input signal from a first format to a second format, the converter comprising:

a decomposition section;

a converter array operatively coupled to the decomposition section; and

a recombination section operatively coupled to the converter array;

wherein the decomposition section includes;

an input to receive the input signal;

a splitter to divide the input signal into a plurality of signals;

a plurality of signal outputs, each of which provides as an output one of the plurality of signals; and

a clock circuit having a plurality of clock outputs for providing sample clocks to the converter array;

wherein the converter array includes a plurality of converters, each of the converters having a signal input to receive one of the plurality of signals, a clock input to receive one of the sample clocks and an output that provides a converted signal;

wherein at least one of the decomposition section and the recombination section includes filters for filtering either the plurality of signals or the plurality of converted signals; and

wherein the decomposition section and recombination section are constructed and arranged to operate on intermediate frequency data.