Semiconductor device

• US 6,341,087 B1
• Filed: 09/25/2000
• Issued: 01/22/2002
• Est. Priority Date: 03/28/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kunikiyo, Tatsuya
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/668,360
• Time in Patent Office: 484 Days
• Field of Search: 365/189.09, 365/226, 365/227, 365/149
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence

Abstract

A body bias generation circuit supplies a body region of a PMOS transistor with a body potential. The body potential is applied so that the body region may be reversely biased or not biased relative to the source region in response to an input signal. The input signal is inputted so that the zero bias may be applied to the body region during standby of the PMOS transistor and the reverse bias may be applied during operation. A body bias generation circuit supplies a body region of an NMOS transistor with a body potential in response to an inverted signal of the input signal. With this constitution, a leak current during standby can be suppressed.

Claims

1. A semiconductor device, comprising:

at least one MOS transistor formed in a main surface of a semiconductor substrate, being a constituent element of a circuit operating in synchronization with a system clock; and

a body bias generation circuit configured to apply a body potential to a body region of said at least one MOS transistor at a different level including a potential of reverse bias relative to a source region in response to a signal of said circuit operating in synchronization with said system clock.

2. The semiconductor device according to claim 1, wherein

said body bias generation circuit selectively applies one of said potential of reverse bias and a potential of zero bias relative to said source region to said body region as said body potential.

3. The semiconductor device according to claim 1, wherein

said body bias generation circuit selectively supplies said body region with one of M (M≧

2) supply currents of different magnitudes.

4. The semiconductor device according to claim 3, wherein said body bias generation circuit comprises:

M oscillator circuits configured to generate M clocks having different frequencies; and

M charge pump circuits configured to intermittently supply said body region with currents individually in synchronization with said M clocks.

5. The semiconductor device according to claim 4, wherein

said body bias generation circuit comprises a monitor circuit configured to compare a difference between a potential of said body region and that of said source region with a reference value and to output a comparison result, and

one of said M oscillator circuits which generates a clock having the highest frequency so operates in response to said comparison result as to generate said clock when said difference is smaller than said reference value.

6. The semiconductor device according to claim 4, wherein

at least one of said M clocks has a frequency higher than that of said system clock.

7. The semiconductor device according to claim 4, wherein

said circuit operating in synchronization with said system clock is a dynamic RAM, and

one of said M oscillator circuits which generates a clock having the lowest frequency comprises a battery backup mode control circuit which judges whether an operating mode of said dynamic RAM is a normal operation mode or a battery backup mode, and generates said clock when it is judged that said operating mode is said normal operation mode and generates said clock only during a refresh request when it is judged that said operating mode is said battery backup mode.

8. The semiconductor device according to claim 1, wherein

said semiconductor substrate is an SOI substrate,

said at least one MOS transistor includes a plurality of MOS transistors of the same conductivity type isolated from one another by partial isolation,

said SOI substrate has a channel stopper doped with an impurity immediately below said partial isolation, and

said body bias generation circuit supplies said body potential in common to said plurality of MOS transistors through said channel stopper.

9. The semiconductor device according to claim 8, wherein

said at least one MOS transistor further includes another MOS transistor which is different in conductivity type from said plurality of MOS transistors, and

said another MOS transistor and at least one of said plurality of MOS transistors adjacent thereto are isolated from each other by full isolation.

10. The semiconductor device according to claim 1, wherein

said semiconductor substrate is an SOI substrate,

said at least one MOS transistor includes M (M≧

2) MOS transistors,

said M MOS transistors are arranged, being divided into N (2≦

N<

M) function blocks, and

said body bias generation circuit is divided into L (2≦

L≦

N) unit body bias generation circuits and said L unit body bias generation circuits individually supply body regions of MOS transistors belonging to L groups selected among said N function blocks with said body potential of reverse bias.

11. The semiconductor device according to claim 10, wherein

at least two function blocks which are adjacent to each other among said N function blocks are isolated from each other by full isolation.

12. The semiconductor device according to claim 1, wherein

said semiconductor substrate is an SOI substrate,

said body bias generation circuit is formed in said main surface, and

said body bias generation circuit and said at least one MOS transistor is isolated from each other by full isolation.

13. The semiconductor device according to claim 1, wherein

said semiconductor substrate is an SOI substrate, and

said SOI substrate has a bottom layer which is positioned immediately below said at least one MOS transistor, being in contact with a surface on the opposite side of said main surface of a buried insulating film and is a semiconductor layer in which an impurity is introduced.

14. The semiconductor device according to claim 13, further comprising:

a bottom potential generation circuit configured to selectively apply a potential of reverse bias relative to a source region of a MOS transistor positioned immediately above said bottom layer to said bottom layer.

15. The semiconductor device according to claim 14, wherein

said bottom potential generation circuit selectively applies one of said potential of reverse bias and the same potential as that of said source region of said MOS transistor positioned immediately above said bottom layer to said bottom layer.

16. The semiconductor device according to claim 14, wherein

said bottom potential generation circuit applies said potential in synchronization with said body bias generation circuit.

17. The semiconductor device according to claim 13, wherein

said body bias generation circuit supplies said bottom layer with a potential supplied to said body region at the same time.