Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode

• US 6,346,451 B1
• Filed: 06/30/1999
• Issued: 02/12/2002
• Est. Priority Date: 12/24/1997
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Simpson, Mark, Letavic, Theodore
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): BERRY, RENEE R
• Application Number:
  US09/343,912
• Time in Patent Office: 958 Days
• Field of Search: 438/311, 438/186, 257/488, 257/285, 257/287, 257/134, 257/138, 257/139
• US Class Current: 438/311
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical

Abstract

A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region. In order to provide improved breakdown voltage characteristics, a dielectric layer is provided over at least a part of the insulation region and the gate electrode, and a field plate electrode is provided over at least a part of the dielectric layer which is in direct contact with the insulation region, with the field plate electrode being connected to an electrode of the lateral transistor device.

Claims

1. A lateral thin-film Silicon-On-Insulator (SOI) device comprising a semiconductor substrate, a buried insulating layer on said substrate, and a lateral transistor device in an SOI layer on said buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, a lateral drift region of said first conductivity type adjacent said body region, a drain region of said first conductivity type and laterally spaced apart from said body region by said lateral drift region, and a gate electrode over a part of said body region in which a channel region is formed during operation and extending over a part of said lateral drift region adjacent said body region, said gate electrode being at least substantially insulated from said body region and drift region by an insulation region, further comprising a dielectric layer over at least a part of said insulation region and said gate electrode, and a field plate electrode over at least a part of said dielectric layer which is in direct contact with said insulation region, said field plate electrode being connected to an electrode of said lateral transistor device.

2. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 1, wherein a total thickness of said dielectric layer and said insulation region is about equal to a thickness of said buried insulation layer.

3. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said total thickness and said thickness are each at least above about 2 microns.

4. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said gate electrode extends over about one half of said lateral drift region.

5. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said field plate electrode is connected to the gate electrode of said lateral transistor device.

6. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said field plate electrode is connected to the source electrode of said lateral transistor device.

7. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said gate electrode comprises polysilicon, said field plate electrode comprises metal, said insulation region comprises a thermal oxide and said dielectric layer comprises a deposited dielectric.

8. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said lateral transistor device comprises a LDMOS transistor.

9. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said lateral transistor device comprises an LIGB transistor.

10. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 2, wherein said lateral transistor device comprises a JFET.

11. A lateral thin-film Silicon-On-Insulator (SOI) device as in claim 1, wherein a total thickness of said dielectric layer and said insulation region and a thickness of said buried insulation layer are selected such that, at any lateral position along the SOI layer, a vertical electric field at the surface of the SOI layer will be about equal to or less than a vertical electric field at the bottom of the SOI layer adjacent to the buried insulting layer.