Phase locked loop with high-speed locking characteristic
DCFirst Claim
1. A phase/frequency detector for comparing a phase/frequency of a reference signal having a reference frequency and that of a feedback signal having a feedback frequency in a phase locked loop (PLL), comprising:
- a NAND gate logic circuit for NANDing a first signal first signal and a second signal to output a NANDed signal;
a first latch means for latching the NANDed signal and outputting the first signal in response to the reference signal; and
a second latch means for latching the NANDed signal and outputting the second signal in response to the feedback signal.
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Abstract
A phase locked loop (PLL) is use in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.
25 Citations
15 Claims
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1. A phase/frequency detector for comparing a phase/frequency of a reference signal having a reference frequency and that of a feedback signal having a feedback frequency in a phase locked loop (PLL), comprising:
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a NAND gate logic circuit for NANDing a first signal first signal and a second signal to output a NANDed signal;
a first latch means for latching the NANDed signal and outputting the first signal in response to the reference signal; and
a second latch means for latching the NANDed signal and outputting the second signal in response to the feedback signal. - View Dependent Claims (2, 3, 4)
a first PMOS transistor, coupled between a power terminal and a node, whose gate receives the first signal;
a second PMOS transistor, coupled between a power terminal and the node, whose gate receives the second signal;
a first NMOS transistor having a drain coupled to the node and a gate receiving the first signal; and
a second NMOS transistor having a drain coupled to a drain of the first NMOS transistor, a source coupled to a ground terminal and a gate receiving the second signal.
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3. The phase/frequency detector as recited in claim 2, wherein the first latch means includes:
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a third PMOS transistor having a source coupled to the power terminal and a gate receiving the NANDed signal;
a third NMOS transistor having a drain coupled to a drain of the third PMOS transistor, a source coupled to the ground terminal and a gate receiving the reference signal;
a fourth PMOS transistor having a source coupled to the power terminal and a gate receiving the reference signal; and
a fourth NMOS transistor having a drain coupled to a drain of the fourth PMOS transistor, a source coupled to the ground terminal and a gate coupled to the drain of the third PMOS transistor.
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4. The phase/frequency detector as recited in claim 3, wherein the second latch means includes:
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a fifth PMOS transistor having a source coupled to the power terminal and a gate receiving the NANDed signal;
a fifth NMOS transistor having a drain coupled to a drain of the fifth PMOS transistor, a source coupled to the ground terminal and a gate receiving the feedback signal;
a sixth PMOS transistor having a source coupled to the power terminal and a gate receiving the feedback signal; and
a sixth NMOS transistor having a drain coupled to a drain of the sixth PMOS transistor, a source coupled to the ground terminal and a gate coupled to the drain of the fifth PMOS transistor.
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5. A phase locked loop (PLL) comprising:
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a phase/frequency detection means for comparing a phase/frequency of a reference signal having a predetermined reference frequency with that of a feedback signal having a predetermined feedback frequency to generate a up pulse and a down pulse according to a phase/frequency difference, wherein the phase/frequency detection means includes two latch circuits and one NAND gate;
a charge pump means for providing a positive pump current signal and a negative pump current signal in response to the up pulse and the down pulse;
a filter means for converting the positive pump current signal and the negative pump current signal into corresponding voltage signal; and
a voltage controlled oscillation means for receiving the voltage signal to generate an output signal having a predetermined oscillation frequency. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
a NAND gate for NANDing a first output of a first latch circuit and a second output of a second latch circuit;
a first latch circuit for receiving and latching an output signal of the NAND gate to output the up pulse in response to the reference signal; and
a second latch circuit for receiving and latching the output signal of the NAND gate and outputting the down pulse in response to the feedback signal.
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8. The phase locked loop (PLL) as recited in claim 7, wherein the first latch circuit includes:
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a first PMOS transistor having a source coupled to a power terminal and a gate receiving the output signal of the NAND gate;
a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor, a gate receiving the reference signal, and a source coupled to a ground terminal;
a second NMOS transistor having a gate coupled to the drain of the first NMOS transistor and a source coupled to the ground terminal; and
a second PMOS transistor having a source coupled to the power terminal, a gate receiving the reference signal, and a drain coupled to the drain of the second NMOS transistor, wherein the up pulse signal is outputted from the drain of the second PMOS transistor.
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9. The phase locked loop (PLL) as recited in claim 7, wherein the second latch means includes:
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a first PMOS transistor having a source coupled to a power terminal and a gate receiving the output signal of the NAND gate;
a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor, a gate receiving the feedback signal, and a source coupled to a ground terminal;
a second NMOS transistor having a gate coupled to the drain of the first NMOS transistor and a source coupled to the ground terminal; and
a second PMOS transistor having a source coupled to the power terminal, a gate receiving the feedback signal, and a drain coupled to the drain of the second NMOS transistor, wherein the down pulse is outputted from the drain of the second PMOS transistor.
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10. The phase locked loop (PLL) as recited in claim 7, wherein the NAND gate includes:
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a first PMOS transistor, coupled between a power terminal and a node, having a gate receiving the up pulse;
a first PMOS transistor, coupled between the power terminal and the node, having a gate receiving the down pulse;
a first NMOS transistor having a drain coupled to the node and a gate receiving the up pulse; and
a second NMOS transistor having a drain coupled to a source of the first NMOS transistor, a gate receiving the down pulse, and a source coupled to the ground terminal.
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11. The phase locked loop (PLL) as recited in claim 5, further comprising a filter control means for performing a switching operation in response to the up pulse and the down pulse, thereby changing a resistance of the filter means.
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12. The phase locked loop (PLL) as recited in claim 11, wherein the filter control means includes:
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an Exclusive-OR (XOR) gate for XORing the up pulse and the down pulse to output a control signal; and
a switching circuit for performing a switching operation in response to the control signal.
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13. The phase locked loop (PLL) as recited in claim 12, wherein the XOR gate includes:
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a first PMOS transistor having a source coupled to a power terminal and a gate receiving the up pulse; and
a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor, a gate receiving the up pulse, and a source coupled to a ground terminal;
a second PMOS transistor having a source coupled to the up pulse and a gate receiving the down pulse;
a second NMOS transistor having a drain coupled to a drain of the second PMOS transistor, a gate receiving the down pulse and a source coupled to an output of the first inverting unit;
a third PMOS transistor having a source coupled to an output of the second inverting unit, a gate receiving the up pulse, and a drain coupled to the down pulse; and
a third NMOS transistor having a drain coupled to the source of the third PMOS transistor, a gate receiving the output of the first inverting unit, and a drain coupled to the down pulse.
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14. The phase, locked loop (PLL) as recited in claim 13, wherein the switching unit includes:
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a fourth NMOS transistor having a gate receiving the output signal of the second inverting unit and a source coupled to the ground terminal; and
a resistor coupled to a drain of the fourth NMOS transistor.
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15. The phase locked loop (PLL) as recited in claim 14, wherein the switching unit further comprises a capacitor coupled between the gate of the fourth NMOS transistor and the ground terminal.
Specification