Hardware assist for YUV data format conversion to software MPEG decoder
DCFirst Claim
1. A display controller for receiving video data from a data bus in a component YUV format and storing the video data to a display memory in a pixel video format, the display controller comprising:
- a bus interface, coupled to the data bus, for receiving video data in a component YUV format and corresponding video data addresses within a predetermined address range;
a display memory controller, coupled to said bus interface, for receiving video data in a component YUV format in contiguous successive streams of luminance and chrominance difference data and corresponding video data addresses within a predetermined address range and for storing said video data by directing separate luminance and chrominance difference data into predetermined memory portions according to a predetermined memory aperture so as to store said video data in a pixel video format in a display memory; and
a memory configuration-register coupled to the bus interface and the display memory controller and configured to set addresses for the predetermined memory aperture.
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Abstract
A display controller assists a host processor in decoding MPEG data. The display controller receives YUV data in non-pixel video format from a host CPU and perform the otherwise CPU intensive task of rasterization within the display controller. In addition, the display controller may use its internal BITBLIT engine to copy U and V data from one line in a BITBLIT operation to adjacent lines, so as to replicate U and V data. A byte mask preserves Y data on the adjacent lines from being overwritten. At the end of the BITBLIT operation, the display controller generates a signal indicating that the frame buffer has been filled with new data, and thus display controller automatically switches to reading from the newly written frame buffer.
38 Citations
27 Claims
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1. A display controller for receiving video data from a data bus in a component YUV format and storing the video data to a display memory in a pixel video format, the display controller comprising:
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a bus interface, coupled to the data bus, for receiving video data in a component YUV format and corresponding video data addresses within a predetermined address range;
a display memory controller, coupled to said bus interface, for receiving video data in a component YUV format in contiguous successive streams of luminance and chrominance difference data and corresponding video data addresses within a predetermined address range and for storing said video data by directing separate luminance and chrominance difference data into predetermined memory portions according to a predetermined memory aperture so as to store said video data in a pixel video format in a display memory; and
a memory configuration-register coupled to the bus interface and the display memory controller and configured to set addresses for the predetermined memory aperture. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 23, 24, 25)
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12. A method for assisting decoding of video data partially decoded in a host processor, said method comprising the steps of:
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receiving, in a display controller, video data in a component YUV format and corresponding video data addresses within a predetermined address range, and storing the video data in a pixel video format in a display memory. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
storing chrominance difference data in every other line of each of the plurality of pairs of byte lanes, and replicating, in a bit block transfer engine within the display controller, chrominance data from every other line of the plurality of pairs of byte lanes to a corresponding adjacent line within the plurality of pairs of byte lanes.
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21. The method of claim 20 wherein the bit block transfer engine replicates chrominance data after the display memory controller has completed storing one frame of video data in the display memory.
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22. The method of claim 21 further comprising the step of outputting a signal to a host processor indicating completion of a bit block transfer operation.
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26. An electronically-readable medium storing a program for permitting a computer to perform a method of assisting decoding of video data partially decoded in a host processor, the method comprising the steps of:
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receiving, in a desplay controller, video data in a component YUV format in contiguous successive streams of luminance and chrominance difference data and corresponding video data addresses within a predetermined address range, setting addresses for a predetermined memory aperture by use of a memory configuration register, and storing the video data by directing separate luminance and chrominance difference data into predetermined memory portions according to the predetermined memory aperture so as to store said video data in a pixel video format in a display memory.
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27. A display system for receiving video data from a data bus in a component YUV format and storing the video data to a display memory in a pixel video format, comprising:
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a data bus to supply video data in a component YUV format;
a display memory to store the video data in a pixel video format;
a bus interface, coupled to the data bus, for receiving the video data in a component YUV format and corresponding video data addresses within a predetermined address range;
a display memory controller, coupled to the bus interface, for receiving the video data in a component YUV format in contiguous successive streams of luminance and chrominance difference data and corresponding video data addresses within a predetermined address range and for storing said video data by directing separate luminance and chrominance difference data into predetermined memory portions according to a predetermined memory aperture so as to store the video data in a pixel video format in a display memory, the display memory controller storing Y data in consecutive odd byte locations on succeeding lines in the display memory by performing an address translation on the Y data, the display memory controller further storing U data in every fourth byte location starting with a second byte location and storing V data in every fourth byte location starting with a fourth byte location;
a memory configuration register coupled to the bus interface and the display memory controller and configured to set addresses for the predetermined memory aperture; and
a display to display the video data.
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Specification