High data rate spread-spectrum system and method

  • US 6,353,627 B1
  • Filed: 11/04/1998
  • Issued: 03/05/2002
  • Est. Priority Date: 11/04/1998
  • Status: Expired due to Term
First Claim
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1. A spread-spectrum system for sending data over a communications channel, comprising:

  • a forward-error-correction (FEC) encoder for encoding, with an FEC code, the data as FEC data;

    an interleaver, coupled to said FEC encoder, for interleaving the FEC data as interleaved data;

    a memory, coupled to said interleaver, for storing N bits of interleaved data as stored data, with N a number of bits in a symbol;

    a chip-sequence encoder, coupled to said memory, for selecting, responsive to the N bits of stored data, a chip-sequence signal from 2N chip-sequence signals stored in said chip-sequence encoder, as an output chip-sequence signal of said chip-sequence encoder;

    a transmitter section, coupled to said chip-sequence encoder, for transmitting the output chip-sequence signal as a radio wave, at a carrier frequency, over said communications channel, as a spread-spectrum signal;

    a receiver section, coupled to said communications channel, for translating the spread-spectrum signal to a processing frequency as a received spread-spectrum signal;

    a plurality of product devices, coupled to said receiver section, for multiplying, at the processing frequency, for acquisition, the received spread-spectrum signal by a header chip-sequence signal with each chip-sequence signal having an identical chip sequence as the header chip-sequence signal, each chip-sequence signal having a delay of one-half or one chip, relative to one another and having a different delay from other chip-sequence signals;

    said plurality of product devices for multiplying, after acquisition, the received spread-spectrum signal by the plurality of 2N chip-sequence signals, with each chip-sequence signal from the plurality of 2N chip-sequence signals having a different chip sequence from other chip-sequence signals in the plurality of 2N chip-sequence signals, respectively;

    a plurality of integrators coupled to said plurality of product devices, respectively, for integrating a plurality of products from the plurality of product devices during a period of a chip-sequence signal thereby forming 2N correlators;

    a comparator, coupled to said plurality of integrators, for selecting a largest value from the plurality of integrators;

    a chip-sequence decoder, coupled to said comparator, for decoding the largest value from a respective integrator of said plurality of integrators, into N bits of interleaved data;

    a deinterleaver, coupled to said chip-sequence decoder, for deinterleaving a series of interleaved bits from said chip-sequence decoder, as deinterleaved data; and

    a FEC decoder, coupled to said deinterleaver, for FEC decoding the deinterleaved data as estimated data.

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