Digital data processing system having a data bus and a control bus

• US 6,356,984 B1
• Filed: 06/30/1998
• Issued: 03/12/2002
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hill, David A., Kiser, Paula C., Kirton, Gavin J., Day, William F., Hornacek, Mark J., Hosrom, Michael K., Copeland, Susan L.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US09/107,070
• Time in Patent Office: 1,351 Days
• Field of Search: 711/147, 711/138, 711/156, 711/111, 711/154, 710/131, 709/232, 709/251, 370/352, 370/355, 370/357, 370/362, 370/403, 370/404
• US Class Current: 711/147
• CPC Class Codes: H04L 12/437 Ring fault isolation or reconfiguration for SDH/SONET ring networks H04J3/085

Abstract

A digital data processing system comprises at least one subsystem comprising a plurality of resources, such as a storage subsystem comprising a plurality of drive modules, and a host processor. The host processor is connected to the drive modules through an interconnection which has a topology in the form of a loop. The interconnection has at least one configuration switch that is selectively configurable to a pass-through mode, in which the topology comprises the entire loop, or a bypass mode, in which the topology comprises a portion of the loop including the host processor and, possibly, at least one of the drive modules in the storage subsystem. The host processor can selectively condition the configuration switch into the pass-through mode or said bypass mode to connect more or fewer drive modules into the loop. Each of the disk modules further includes a disk module and a port by-pass switch, the port by-pass switch also being selectively configurable to a pass-through mode, in which the topology of the interconnection includes the disk module, and a bypass mode, in which the topology of the interconnection bypasses the disk module. The host processor can selectively condition the port bypass switches of the disk modules to connect more or fewer disk modules into the loop. The configuration switch and the port by-pass switches are directly controlled by a subsystem controller, which receives commands for controlling the switches from the host processor over a separate command interconnection.

Claims

1. A digital data processing system, comprising:

a first host;

a first storage subsystem comprising a first plurality of storage devices;

a data bus connected to the first host and the first storage subsystem for transmitting data between the first host and the first plurality of storage devices in the first storage subsystem; and

a control bus connected to the first host and the first storage subsystem for transmitting control signals from the first host to the first storage subsystem and for transmitting status responses from the first storage subsystem to the first host.

2. The digital data processing system of claim 1, wherein the storage subsystem is configured to disconnect one of the first plurality of storage devices from the data bus in response to configuration commands provided by the first host while continuing to connect the remainder of the first plurality of storage devices to the data bus.

3. The digital data processing system of claim 1, wherein:

the data bus has a loop topology; and

the first storage subsystem includes a first configuration switch, the first configuration switch having a pass-through mode, in which the loop topology connects the first plurality of storage devices to the data bus, and a bypass mode, in which the loop topology connects a subset of the plurality of devices to the data bus;

wherein the first configuration switch is configured to change from the pass-through mode to the bypass mode in response to a bypass command received by the first storage subsystem from the control bus.

4. The digital data processing system of claim 1, wherein said control bus transmits said control signals and said status responses in the form of packets.

5. The digital data processing system of claim 4, wherein said packets comprise:

a start field indicating the beginning of the packet;

a target address field identifying an intended recipient of the packet;

a source address field identifying an initiator of the packet;

a checksum field; and

an end field indicating the end of the packet.

6. The digital data processing system of claim 5, wherein said packets further comprise an operation code field indicating an operation to be performed by the recipient of the packet.

7. The digital data processing system of claim 5, wherein said packets further comprise a data field containing a message or command.

8. The digital data processing system of claim 7, wherein said packets further comprise a length field indicating the size of the data field.

9. The digital data processing system of claim 1, wherein:

said first host is configured to transmit an attention command control signal via the control bus to the first storage subsystem, said attention command control signal instructing the first storage subsystem to transmit a status response indicating the status of one of the plurality of storage devices.

10. The digital data processing system of claim 1, further comprising one or more additional hosts, each of said one or more additional hosts being connected to the first storage subsystem via the control bus and the data bus.

11. The digital data processing system of claim 1, wherein at least one of the storage devices in the first plurality of storage devices comprises a disk storage device.

12. The digital data processing system of claim 1, wherein said first storage subsystem further comprises a first subsystem controller connected to the control bus, said first subsystem controller configured to receive the control signals from the first host via the control bus and to transmit status responses to the first host via the control bus.

13. The digital data processing system of claim 1, wherein the control bus comprises an I₂C bus.

14. A method of operating a digital data processing system, comprising:

connecting a first host to a first storage subsystem comprising a first plurality of storage devices via a data bus and a control bus;

transmitting data via the data bus between the first host and the first storage subsystem;

transmitting control signals via the control bus from the first host to the first storage subsystem; and

transmitting status responses via the control bus from the first storage subsystem to the first host.

15. The method of claim 14, further comprising:

transmitting a configuration command via the control bus from the first host to the first storage subsystem; and

in response to receiving the configuration command from the first host, the first storage subsystem disconnects one of the first plurality of storage devices from the data bus while continuing to connect the remainder of the first plurality of storage devices to the data bus.

16. The method of claim 14, further comprising:

transmitting data along the data bus, said data bus having a loop topology;

transmitting a bypass command via the control bus from the first host to the first storage subsystem; and

in response to receiving the bypass command, the first storage subsystem switches from a pass-through mode, in which the loop topology connects the first plurality of storage devices to the data bus, to a bypass mode, in which the loop topology connects a subset of the plurality of devices to the data bus.

17. The method of claim 14, further comprising:

transmitting the control signals from the first host in packet form; and

transmitting the status responses from the first storage subsystem in packet form.

18. The method of claim 17, wherein said packets comprise:

a start field indicating the beginning of the packet;

a target address field identifying an intended recipient of the packet;

a source address field identifying the initiator of the packet;

a checksum field; and

an end field indicating the end of the packet.

19. The method of claim 18, wherein said packets further comprise an operation code field indicating an operation to be performed by the recipient of the packet.

20. The method of claim 18, wherein said packets further comprise a data field containing a message or command.

21. The method of claim 20, wherein said packets further comprise a length field indicating the size of the data field.

22. The method of claim 14, further comprising:

transmitting an attention command control signal via the control bus from the first host to the first storage subsystem; and

in response to receiving the attention command control signal, transmitting a status response via the control bus from the first storage subsystem to the first host, said status response indicating the status of said one of the plurality of storage devices.

23. The method of claim 14, further comprising:

connecting a second host to the first storage subsystem via the data bus and the control bus;

transmitting data via the data bus between the second host and the first plurality of storage devices in the first storage subsystem;

transmitting control signals via the control bus from the first host to the first storage subsystem; and

transmitting status responses via the control bus from the first storage subsystem to the second host.

24. The method of claim 14, wherein at least one of the storage devices in the first plurality of storage devices comprises a disk storage device.

25. The method of claim 14, wherein:

receiving the control signals from the first host with a first subsystem controller provided in the first storage subsystem; and

transmitting the status responses to the first host with the first subsystem controller.