Computerized method and apparatus for designing wire bond diagrams and locating bond pads for a semiconductor device

• US 6,357,036 B1
• Filed: 04/29/1999
• Issued: 03/12/2002
• Est. Priority Date: 10/02/1998
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Martinez, Marcello R. III, Eka, Laiman, Fong, Carl H.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/301,691
• Time in Patent Office: 1,048 Days
• Field of Search: 716/19, 716/4, 716/15
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements

Abstract

The present invention provides a bond tool utility software package which extracts bond pad location data from a semiconductor chip design stored in one of a number of known formats (e.g., Opus, GDSII, or the like) and extracts conductor location data from an AUTOCAD file of a chip frame design. The utility retrieves bonding connection data from a design ASCII file and generates a bonding diagram for the semiconductor assembly. The utility also contains a subroutine for applying bonding design criteria to the resultant bonding diagram to determine whether all bonds are within established guidelines. If an impermissible bond is formed, the user may be alerted that one or more bonding pads may have to be relocated. In one embodiment of the present invention, the bonding utility may interface with a semiconductor design circuit to generate a suggested fix to an impermissible bonding situation. One or more bonding pads may be moved in the semiconductor design to correct for potential bonding deficiencies.

Claims

1. A computerized automatic method for generating a wire bonding diagram for a semiconductor device, said method comprising the steps of:

generating, in a computer, pad layer coordinates and pin assignments from semiconductor design data;

generating, in a computer, package information from semiconductor package drawing information;

generating, in a computer, wire bonding diagram data from the extracted package information and the pad layer coordinates and pin assignments;

automatically checking, with a computer program, the wire bonding diagram data against a design rule database comprising a predetermined set of wire bonding rules to determine whether any wire bonds violate one or more of the predetermined set wire bonding rules;

automatically adjusting location of one or more pads in the semiconductor design in response to any violation of the predetermined set of wire bonding rules; and

automatically generating a bonding diagram database representing locations of wire bonds for the semiconductor device.

2. The method of claim 1, wherein said step of generating pad layer coordinates and pin assignments from semiconductor design data comprises the steps of:

receiving, from a circuit design computer program, a circuit design database representing a circuit design of the semiconductor device;

receiving a pin assignment database representing pin assignments for the semiconductor device; and

extracting, using a computer program, pad layer coordinates and pin assignments from the from the circuit design database and the pin assignment database.

3. The method of claim 2, wherein said step of generating package information from semiconductor package drawing information comprises the steps of:

receiving a drawing database comprising a drawing of a package design for the semiconductor device; and

extracting, using a computer program, package information from the drawing database.

4. The method of claim 2, further comprising the steps of:

outputting adjusted locations of one or more pads in the circuit design adjusted in response to any violation of the predetermined set of wire bonding rules to an interface program;

converting the adjusted locations of the one or more pads into a data format compatible with the circuit design computer program; and

revising the first database to reflect the adjusted locations of the one or more pads.

5. A series of steps to be performed by a computer for generating a bonding diagram for a semiconductor device, comprising the steps of:

generating, from semiconductor design data, a first data file comprising pad layer coordinates of the semiconductor device and pin assignments for a semiconductor package;

generating, from semiconductor package drawing data, a second data file comprising package lead location data;

generating, from the first and second data files, a third data file comprising wire bonding diagram data;

checking the wire bonding diagram data against a design rule database comprising a predetermined set of wire bonding rules to determine whether any wire bonds violate one or more of the predetermined set wire bonding rules;

adjusting location of one or more pads in the wire bonding diagram data in the third data file in response to any violation of the predetermined set of wire bonding rules; and

outputting the wire bonding diagram data in the third data file representing locations of wire bonds for the semiconductor device.

6. The series of steps to be performed by a computer for generating a bonding diagram for a semiconductor device of claim 5, wherein said step of generating the first data file comprises the steps of:

receiving, from a circuit design computer program, a circuit design database representing a circuit design of the semiconductor device;

receiving a pin assignment database representing pin assignments for the semiconductor device; and

extracting pad layer coordinates and pin assignments from the from the circuit design database and the pin assignment database.

7. The series of steps to be performed by a computer for generating a bonding diagram for a semiconductor device of claim 6, wherein said step of generating the second data file comprises the steps of:

receiving a drawing database comprising a drawing of a package design for the semiconductor device; and

extracting package information from the drawing database.

8. The series of steps to be performed by a computer for generating a bonding diagram for a semiconductor device of claim 6, further comprising the steps of:

outputting adjusted locations of one or more pads in the circuit design adjusted in response to any violation of the predetermined set of wire bonding rules to an interface program;

converting the adjusted locations of the one or more pads into a data format compatible with the circuit design computer program; and

revising the first database to reflect the adjusted locations of the one or more pads.

9. An apparatus for generating a wire bonding diagram for a semiconductor device, comprising:

first means for generating pad layer coordinates and pin assignments from semiconductor design data;

second means for generating package information from semiconductor package drawing information;

third means, coupled to said first and second means, for generating wire bonding diagram data from the extracted package information and the pad layer coordinates and pin assignments;

fourth means for checking the wire bonding diagram data against a design rule database comprising a predetermined set of wire bonding rules to determine whether any wire bonds violate one or more of the predetermined set wire bonding rules;

fifth means for adjusting location of one or more pads in the semiconductor design in response to any violation of the predetermined set of wire bonding rules; and

sixth means for generating a bonding diagram database representing locations of wire bonds for the semiconductor device.

10. The apparatus of claim 9, wherein said first means for generating pad layer coordinates and pin assignments from semiconductor design data comprises:

means for receiving, from a circuit design computer program, a circuit design database representing a circuit design of the semiconductor device;

means for receiving a pin assignment database representing pin assignments for the semiconductor device; and

a computer program for extracting pad layer coordinates and pin assignments from the from the circuit design database and the pin assignment database.

11. The apparatus of claim 9, wherein said second means for generating package information from semiconductor package drawing information comprises:

means for receiving a drawing database comprising a drawing of a package design for the semiconductor device; and

a computer program for extracting package information from the drawing database.

12. The apparatus of claim 9, further comprising:

means for outputting adjusted locations of one or more pads in the circuit design adjusted in response to any violation of the predetermined set of wire bonding rules to an interface program;

means for converting the adjusted locations of the one or more pads into a data format compatible with the circuit design computer program; and

means for revising the first database to reflect the adjusted locations of the one or more pads.

13. A computer program for use with semiconductor circuit design program data and computer generated design drafting data of a semiconductor package, the computer program comprising:

a first portion, receiving the semiconductor circuit design program data and a net list pin assignment data file, for extracting pad layer coordinates and pin assignments;

a second portion, receiving the design drafting data of a semiconductor package, for generating package lead location information;

a third portion, receiving the extracted pay layer coordinates and pin assignments and package lead location information and generating wire bonding diagram data;

a fourth portion, receiving the wire bonding diagram data and checking the wire bonding diagram data against a design rule database comprising a predetermined set of wire bonding rules to determine whether any wire bonds violate one or more of the predetermined set wire bonding rules; and

a fifth portion, for adjusting location of one or more pads layer coordinates in response to any violation of the predetermined set of wire bonding rules.

14. The computer program of claim 13, wherein said first portion comprises:

means for receiving, from a semiconductor circuit design computer program, the semiconductor circuit design program data representing a circuit design of the semiconductor device;

means for receiving a pin assignment database representing pin assignments for the semiconductor device; and

means for extracting pad layer coordinates and pin assignments from the from the semiconductor circuit design program data and the pin assignment database.

15. The computer program of claim 14, wherein said second portion comprises:

means for receiving a drawing database comprising a drawing of a package design for the semiconductor device; and

means for extracting package lead location information from the drawing database.

16. The computer program of claim 13, further comprising:

a sixth portion for outputting adjusted locations of one or more pad layer coordinates in the circuit design adjusted in response to any violation of the predetermined set of wire bonding rules to an interface program;

a seventh portion for converting the adjusted locations of the one or more pad layer coordinates into a data format compatible with the semiconductor circuit design computer program data; and

means for revising the semiconductor circuit design program data reflect adjusted locations of the one or more pad layer coordinates.