Instruction cache associative crossbar switch

  • US 6,360,313 B1
  • Filed: 09/08/2000
  • Issued: 03/19/2002
  • Est. Priority Date: 11/05/1993
  • Status: Expired due to Fees
First Claim
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1. In a computing system having a plurality of processing pipelines in which groups of individual instructions, within a very long instruction word, are executable by the plurality of processing pipelines, individual instructions in the very long instruction word to be executed having associated therewith group identifiers and pipeline identifiers, an apparatus for routing each individual instruction of a group of individual instructions to be executed in parallel to an appropriate processing pipeline of the plurality of processing pipelines, the apparatus comprising:

  • a main memory for storing the very long instruction word;

    a very long instruction word storage coupled to the main memory, for receiving the very long instruction word from the main memory and for holding the very long instruction word the very long instruction word including groups of instructions to be executed in parallel, including pipeline identifiers and group identifiers;

    a selection circuit coupled to the very long instruction word storage for receiving the group identifiers included in the very long instruction word, for determining in response thereto a group of individual instructions to be executed in parallel, and for outputting a control signal;

    a decoder circuit coupled to the selection circuit and to the very long instruction word storage, for receiving the control signal and the pipeline identifiers included in the very long instruction word, for determining in response thereto the appropriate processing pipeline for each individual instruction of the group, and for outputting switch control signals;

    a switching circuit coupled to the decoder circuit, having a first set of connectors coupled to the very long instruction word storage for receiving the very long instruction word therefrom and a second set of connectors coupled to the plurality of processing pipelines, for coupling each individual instruction of the group to an appropriate processing pipeline in response to the switch control signals.

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