Collimated sputtering of semiconductor and other films

• US 6,362,097 B1
• Filed: 07/14/1998
• Issued: 03/26/2002
• Est. Priority Date: 07/14/1998
• Status: Expired due to Fees

• Current Assignee: Applied Komatsu Technology, Inc., Applied Materials Incorporated
• Original Assignee: Applied Komatsu Technology, Inc.
• Inventors: Pethe, Rajiv Gopal, Demaray, Richard Ernest, Deshpandey, Chandra
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/115,258
• Time in Patent Office: 1,351 Days
• Field of Search: 438/658, 438/46, 438/622, 438/632, 438/655, 438/646, 438/482, 438/589, 438/641, 438/647, 438/674, 438/764, 438/766, 438/771, 438/792, 438/763, 438/702, 294/47, 204/192.12, 204/192.11, 204/298, 257/412, 257/315, 257/377, 257/775, 257/522, 427/573
• US Class Current: 438/674
• CPC Class Codes: C23C 14/34 Sputtering
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed. Dielectric films having a thickness as small as several hundred Å can be formed to fabricate high transconductance devices with high breakdown strengths. improved electrically active interfaces, such as a rectifying junction between a semiconductor layer and a dielectric layer or an ohmic junction between intrinsic and doped semiconductor materials.

Claims

1. A method of depositing a layer of a silicon-containing material, the method comprising:

providing a substrate in an evacuable chamber, wherein the substrate includes a glass plate;

providing a target comprising semiconducting silicon in the chamber spaced from the substrate;

sputtering the target with a gas plasma; and

collimating trajectories of sputtered particles to a surface of the substrate using a collimator having an aspect ratio to form on the substrate surface a film of a silicon-containing material, wherein said sputtering step deposits said film as a semiconducting silicon material.

2. A method of depositing a layer of a silicon-containing material, the method comprising:

providing a substrate in an evacuable chamber;

providing a target comprising silicon in the chamber spaced from the substrate;

sputtering the target with a gas plasma;

collimating trajectories of sputtered particles to a surface of the substrate using a collimator having an aspect ratio to form on the substrate surface a film of a silicon-containing material; and

providing a gaseous supply of dopants in a vicinity of the sputtered material.

3. A method of depositing a layer of a silicon-containing material, comprising:

providing a substrate in an evacuable chamber;

providing a target comprising semiconducting silicon in the chamber spaced from the substrate, wherein the target is a semiconductor silicon-based material containing dopants;

sputtering the target with a gas plasma; and

collimating trajectories of sputtered particles to a surface of the substrate using a collimator having an aspect ratio to form on the substrate surface a film of a silicon-containing material, wherein said sputtering step deposits said film as a semiconducting silicon material.

4. A method of depositing a layer of a dielectric material, the method comprising:

providing a substrate in an evacuable chamber;

providing a target comprising a silicon-based target material in the chamber spaced from the substrate;

sputtering the target material with a gas plasma;

providing a reactive gas in a vicinity of the sputtered target material;

collimating trajectories of sputtered particles to a surface of the substrate using a collimator having an aspect ratio to form on the substrate surface a dielectric material; and

isolating the substrate from electrically charged plasma particles by holding the collimator at a predetermined electrical potential, wherein the dielectric layer formed on the substrate has a trapped charge density of less than 1×

10¹¹ per cm².

5. The method of claim 4 wherein the dielectric layer has a thickness of less than about 100 nm.

29. The method of claim 4, wherein the dielectric material comprises silicon oxide.

6. A method of depositing a layer of a dielectric material forming an optical film, the method comprising:

providing a substrate in an evacuable chamber;

providing a target material in the chamber spaced from the substrate;

sputtering the target material with a gas plasma;

providing a reactive gas in a vicinity of the sputtered target material; and

collimating trajectories of sputtered particles to a surface of the substrate using a collimator having a plurality of holes extending therethrough along respective axes perpendicular to a principal surface of said substrate to form on the substrate surface a dielectric material forming said optical film.

7. The method of claim 6 wherein the dielectric material comprises a silicon compound selected from the group consisting of silicon nitride and silicon oxide.

8. A method of fabricating an operable electronic device having an electrically active junction, the method comprising:

forming a horizontally extending semiconductor layer and forming a horizontally extending dielectric layer in a vertical structure with a horizontally extending interface therebetween, wherein at least the semiconductor layer is formed by collimated sputtering, and wherein the semiconductor and dielectric layers are disposed vertically adjacent and contacting one another to form the electrically active junction of the operable electronic device across said horizontally extending interface.

9. The method of claim 8 wherein forming the semiconductor layer includes:

sputtering a target of a semiconductor material with a gas plasma; and

collimating trajectories of sputtered semiconductor material particles toward a substrate using a collimator having an aspect ratio to form a film of the semiconductor material.

10. A method of fabricating an operable electronic device having an electrically active junction, the method comprising forming a semiconductor layer and forming a dielectric layer in a vertical structure,

wherein at least the semiconductor layer is formed by collimated sputtering, and wherein the semiconductor and dielectric layers are disposed vertically adjacent and contacting one another to form the electrically active junction of the operable electronic device, and

wherein forming said dielectric layer includes:

sputtering a target material with a gas plasma;

providing a reactive gas in a vicinity of the sputtered material; and

collimating trajectories of sputtered particles toward a substrate with a collimator having a plurality of holes extending therethrough along respective axes perpendicular to a principal surface of said substrate in which said electronic devices are fabricated.

22. The method of any one of claims 4, 9, 10, 11, 15, 16, 19, 20 or 21 further including isolating the substrate from electrically charged plasma particles.

23. The method of claim 22 wherein isolating the substrate includes grounding the collimator.

24. The method of any one of claims 4, 9, 10, 11, 15, 16, 19, 20 or 21 further including isolating the substrate from electrically charged plasma particles to reduce creation of charge defects in films formed by collimated sputtering.

11. A method of fabricating a transistor, the method comprising:

sputtering a target of a semiconductor material with a gas plasma;

collimating trajectories of sputtered semiconductor material particles toward a substrate using a first collimator having a first aspect ratio to form a layer of semiconductor material; and

forming a dielectric layer adjacent the semiconductor layer using collimated sputtering;

wherein an interface between the semiconductor and dielectric layers forms an electrically active junction of the transistor.

12. The method of claim 11 wherein forming said dielectric layer includes:

sputtering a target material with a gas plasma;

providing a reactive gas in a vicinity of the sputtered target material; and

collimating trajectories of sputtered material particles to a surface of the substrate using a second collimator having a second aspect ratio to form on the substrate surface a dielectric material.

13. The method of claim 11 further including:

forming doped semiconductor source and drain regions for the transistor using collimated sputtering.

14. A method of fabricating an operable electronic device having an electrically active junction, the method comprising:

forming in a vertical structure an intrinsic semiconductor layer and a doped semiconductor layer of a first conductivity type, wherein at least one of the intrinsic and doped layers is formed using collimated sputtering and wherein the intrinsic and doped layers are disposed vertically adjacent and contacting one another to form therebetween the electrically active junction of the operable electronic device.

15. The method of claim 14 wherein forming an intrinsic semiconductor layer includes:

sputtering a target of a semiconductor material with a gas plasma; and

collimating trajectories of sputtered semiconductor material particles toward a substrate using a collimator having an aspect ratio to form a film of the semiconductor material.

16. A method of fabricating an electronic device having an electrically active junction, the method comprising forming in a vertical structure an intrinsic semiconductor layer and a doped semiconductor layer of a first conductivity type,

wherein at least one of the intrinsic and doped layers is formed using collimated sputtering,

wherein the intrinsic and doped layers are disposed vertically adjacent one another to form the electrically active junction therebetween, and

wherein forming a doped semiconductor layer includes:

sputtering a target of a doped semiconductor material with a gas plasma; and

collimating trajectories of sputtered doped semiconductor material particles toward a substrate using a collimator having an aspect ratio to form a film of the doped semiconductor material.

17. A method of fabricating an electronic device having an electrically active junction, the method comprising forming in a vertical structure an intrinsic semiconductor layer and a doped semiconductor layer of a first conductivity type,

wherein at least one of the intrinsic and doped layers is formed using collimated sputtering,

wherein the intrinsic and doped layers are disposed vertically adjacent one another to form the electrically active junction therebetween, and

wherein forming a doped semiconductor layer includes:

sputtering a target of an intrinsic semiconductor material with a gas plasma;

providing a gaseous supply of dopants in a vicinity of the sputtered semiconductor material; and

collimating trajectories of sputtered semiconductor material particles toward a substrate using a collimator having an aspect ratio to form a film of the doped semiconductor material.

18. A method of fabricating an opto-electronic device for emitting or detecting light, the method comprising:

forming an intrinsic semiconductor layer;

forming a first semiconducting layer of a first conductivity type on one side of the intrinsic semiconductor layer; and

forming a second semiconducting layer of a second conductivity type opposite the first conductivity type on a second side of the intrinsic semiconductor layer;

wherein an interface between the first semiconducting layer and the intrinsic layer forms a first electrically active junction of the opto-electronic device and an interface between the intrinsic layer and the second semiconducting layer forms a second electrically active junction of the opto-electronic device, and

wherein at least one of the intrinsic semiconductor layers, the first semiconducting layer and the second semiconducting layer is formed using collimated sputtering.

19. The method of claim 18 wherein forming an intrinsic semiconductor layer includes:

sputtering a target of an intrinsic semiconductor material with a gas plasma; and

collimating trajectories of sputtered semiconductor particles toward a substrate using a collimator having an aspect ratio to form a film of the semiconductor material.

20. The method of claim 18 wherein forming the first semiconducting layer of said first conductivity type includes:

sputtering a target of a semiconductor material of the first conductivity type with a gas plasma; and

collimating trajectories of particles of the sputtered semiconductor material toward a substrate using a collimator having an aspect ratio to form a film of the semiconductor material.

21. The method of claim 18 wherein forming the first semiconductor layer of said first conductivity type includes:

sputtering a target of an intrinsic semiconductor material with a gas plasma;

providing a gaseous supply of dopants in a vicinity of the sputtered semiconductor material; and

collimating trajectories of sputtered semiconductor material particles toward a substrate suing a collimator having an aspect ratio to form a film of doped semiconducting material.

25. A method of forming a flat panel display, the method comprising:

providing a substrate including a glass plate;

forming a first dielectric layer on a surface of the substrate by collimated sputtering;

forming a second dielectric layer on selected regions of the first dielectric layer, wherein areas that include the second dielectric layer form pixel regions, and wherein areas without the second dielectric form non-pixel regions;

forming memory devices on the pixel regions; and

forming high transconductance devices on the first dielectric layer.

26. The method of claim 25 wherein forming a second dielectric layer includes forming the second dielectric layer by collimated sputtering.

27. The method of claim 25 wherein forming memory devices includes forming transistors on the pixel regions, and wherein forming transistors includes:

forming a semiconductor layer adjacent a dielectric layer by collimated sputtering to form electrically active junctions of the transistors.

28. The method of claim 27 wherein forming a semiconductor layer includes:

sputtering a target of a semiconductor material with a gas plasma; and

collimating trajectories of sputtered semiconductor material particles toward the substrate using a collimator having an aspect ratio to form the layer of semiconductor material.

30. The method of claim 25, wherein said first dielectric layer comprises a silicon-containing dielectric selected from the group consisting of silicon nitride and silicon oxide.