Borderless vias on bottom metal

  • US 6,362,527 B1
  • Filed: 11/21/1996
  • Issued: 03/26/2002
  • Est. Priority Date: 11/21/1996
  • Status: Expired due to Term
First Claim
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1. An integrated circuit having a plurality of semiconductor devices therein and a multilevel metallization structure for interconnection of said semiconductor devices thereon, said multilevel metallization structure comprising:

  • a plurality of substantially parallel, separated, patterned metal layers including a first bottom metal layer and a second top metal layer, said first bottom metal layer being separated from said top metal layer by an ILD layer therebetween, each of said patterned metal layers being comprised of metal lines separated by gaps;

    said ILD layer between said first bottom metal layer and said second top metal layer having vias therethrough, said vias having conducting via plugs therein, said via plugs providing electrical connectivity between said first bottom metal layer and said top metal layer;

    said bottom metal layer having therein at least one bottom metal line having a top conducting surface and an edge surface, said bottom metal line being surrounded by a dielectric layer having a top dielectric surface, said top conducting surface and said top dielectric surface being substantially locally coplanar near said bottom metal line, a first portion of said top dielectric surface not being coincident with said vias, and a first portion of said top conducting metal surface not being coincident with said vias;

    said first portion of said top dielectric surface not coincident and said first portion of said top conducting metal surface not coincident having thereon a thin non-conducting via etch-stop layer under said ILD.

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