Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
DC
First Claim
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1. An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles, wherein said circuit is enabled or disabled in response to an enable signal.
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Abstract
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
109 Citations
24 Claims
- 1. An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles, wherein said circuit is enabled or disabled in response to an enable signal.
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11. A method for reducing power consumption in a synchronous integrated circuit comprising the steps of:
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(A) detecting if one or more chip select signals has been in a first state for a predetermined number of clock cycles; and
(B) automatically generating a Jedec-standard “
ZZ”
signal when said one or more chip select signals has been in said first state for said predetermined number of clock cycles.- View Dependent Claims (12, 13, 14)
generating one or more internal select signals corresponding to said one or more chip set signgnals.
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13. The method according to claim 11, wherein said Jedec-standard “
- ZZ”
signal is automatically generated in response to a clock signal.
- ZZ”
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14. The method according to claim 13, further comprising the sub-steps of:
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when a control signal is in a first state, counting a number of pulses of said clock signal;
when said number of pulses counted reaches a predetermined value, setting said Jedec-standard “
ZZ”
signal to a first predetermined state; and
when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said Jedec-standard “
ZZ”
signal to a second predetermined state.
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15. An apparatus comprising a circuit configured to automatically generate a Jedec-standard “
- ZZ”
signal upon detecting that one or more chip select signals have been in a first state for a predetermined number of clock cycles. - View Dependent Claims (16, 17, 18, 19, 20)
- ZZ”
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21. A method for reducing power consumption in a synchronous integrated circuit comprising the steps of:
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counting a number of pulses of said clock signal when a control signal is in a first state;
when said number of pulses counted reaches a predetermined value, automatically setting a sleep signal to a first predetermined state; and
when said control signal is in a second state, (i) resetting said number of pulses counted and/or (ii) setting said sleep signal to a second predetermined state. - View Dependent Claims (22, 23, 24)
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Specification
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Litigation Data
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Current AssigneeMonterey Research, LLC (Vector Capital Corporation)
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsPhelan, Cathal
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Primary Examiner(s)Hoang, Huan
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Application NumberUS09/747,790Publication NumberTime in Patent Office459 DaysField of Search365/233, 365/229, 365/236, 365/189.05US Class Current365/233.1CPC Class CodesG11C 5/14 Power supply arrangements ,...
