Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

  • US 6,363,031 B2
  • Filed: 12/22/2000
  • Issued: 03/26/2002
  • Est. Priority Date: 11/03/1999
  • Status: Expired due to Term
First Claim
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1. An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles, wherein said circuit is enabled or disabled in response to an enable signal.

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