Staged partitioned communication bus for a multi-port bridge for a local area network

• US 6,363,067 B1
• Filed: 03/19/1999
• Issued: 03/26/2002
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Chung, David
• Primary Examiner(s): Nguyen, Chau T.
• Assistant Examiner(s): TRINH, DUNG N
• Application Number:
  US09/272,829
• Time in Patent Office: 1,103 Days
• Field of Search: 370/364, 370/401, 370/402, 370/274, 370/315, 370/407, 370/408, 370/425
• US Class Current: 370/364
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40143 involving priority mechanisms hybrid switching fabrics H04L12/6402; intermediate storage or scheduling H04L49/90; time-division multiplex systems H04J3/00
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/135 by jamming the transmission media
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

A staged partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of data bus segments. Each data bus segment is coupled to one or more ports of the multi-port bridge and includes a same number of signal lines. A multiplexer is coupled to each data bus segment and to a memory device. A bus controller is coupled to each port and to the multiplexer. Each port requests access to the memory device from the bus controller for storing packets in the memory device and for retrieving packets therefrom. In response, the bus controller conditions the multiplexer to provide a signal path between the memory device to and the data bus segment which includes the requesting port. The memory device temporarily stores packets undergoing communication between the ports. Accordingly, a source port for a packet transfers the packet to the memory device via the multiplexer and, then, a destination port for the packet retrieves the packet from the memory device via the multiplexer. If the source port and the destination port are on a same data bus segment and the destination port is not currently busy, the destination port receives the packet directly from the source port as the source port stores the packet in the memory device. A look-up bus can be included, which is operable independently of the staged partitioned bus, for correlating destination addresses for packets to identifications of destination ports.

Claims

1. An apparatus having a staged partitioned bus for transferring data, the apparatus comprising:

a. a first bus segment having a first plurality of (n) signal lines and coupled to a first plurality of ports;

b. a second bus segment having a second plurality of (n) signal lines and coupled to a second plurality of ports;

c. a multiplexer coupled to the first bus segment and the second bus segment;

d. memory means coupled to the multiplexer for temporarily storing data undergoing communication between the first bus segment and the second bus segment

e. a first port among the first plurality of ports;

f. a second port among the second plurality of ports; and

g. a control means coupled to the multiplexer wherein the control means selectively conditions the multiplexer to provide access to the memory means by the first port and by the second port.

2. The apparatus according to claim 1 wherein the first port and the second port are respectively configured to request access to the memory means from the control means.

3. A multi-port bridge having a staged partitioned bus for transferring data between ports of the multi-port bridge, the multi-port bridge comprising:

a. a first data bus segment having a first plurality of (n) signal lines;

b. a first plurality of ports coupled to the first data bus segment;

c. a second data bus segment having a second plurality of (n) signal lines;

d. a second plurality of ports coupled to the second data bus segment;

e. a multiplexer having a first input coupled to the first data bus segment, a second input coupled to the second data bus segment and an output;

f. a memory device coupled to the output of the multiplexer whereby data is selectively communicated between a first select port within the first plurality of ports and the memory device and between a second select port within the second plurality of ports and the memory device according to a condition of the multiplexer and

g. a controller coupled to the multiplexer to condition the multiplexer.

4. The multi-port bridge according to claim 3 wherein data packets are communicable between the first select port and the second select port by temporary storage of the data packets in the memory device and retrieval therefrom.

5. The multi-port bridge according to claim 4 wherein data packets are communicated between the first select port and the one or more additional ports coupled to the first data bus segment via the first data bus segment without the data packets having to be temporarily stored in, and retrieved from, the memory device.

6. The multi-port bridge according to claim 3 further comprising a look-up bus coupled to the first select port, wherein the first select port is configured to send the look-up table destination addresses of data packets received by the first select port.

7. The multi-port bridge according to claim 6 wherein the look-up table correlates destination addresses for packets to identifications of destination ports.

8. The multi-port bridge according to claim 7 wherein the multi-port bridge is configured to transmit data received from the look-up table to the first select port.

9. The multi-port bridge according to claim 7 wherein the multi-port bridge is configured to transmit a first information packet to a source port in response to a look up operation initiated by the source port.

10. The multi-port bridge according to claim 9 wherein the multi-port bridge is configured to transmit a second information packet to a destination port in response to the look-up operation initiated by the source port.

11. The multi-port bridge according to claim 10 wherein the second information packet transmitted to the destination port comprises a triplet, and wherein the destination port is configured to store the information packet in a request queue.

12. A multi-port bridge having a staged partitioned bus for transferring data between ports of the multi-port bridge, the multi-port bridge comprising:

a. a first data bus segment having a first plurality of (n) signal lines;

b. a first plurality of ports coupled to the first data bus segment;

c. a second data bus segment having a second plurality of (n) signal lines;

d. a second plurality ports coupled to the second data bus segment;

e. a multiplexer coupled to the first data bus segment and to the second data bus segment;

f. a memory device coupled to the multiplexer wherein data is selectively communicable between the first data bus segment and the memory device and between the second data bus segment and the memory device according to a condition of the multiplexer;

g. a look-up bus coupled to each of the first plurality of ports and to each of the second plurality of ports; and

h. a look-up table coupled to the look-up bus to store node addresses in association with port identifications.

13. The multi-port bridge according to claim 12 wherein a destination port for a data packet received by the multi-port bridge is identified by a source port for the data packet, the destination port looking up a destination address for the data packet in the look-up table via the look-up bus.

14. The multi-port bridge according claim 13 wherein when the source port for the data packet is included in the first plurality of ports and the destination port for the data packet is included in the second plurality of ports the data packet is stored in the memory device by the source port and retrieved from the memory device by the destination port.

15. The multi-port bridge according to claim 13 wherein when the source port for the data packet is included in the first plurality of ports and the destination port for the data packet is also included in the first plurality of ports, the destination port receives the data packet from the source port via the first data bus segment.

16. The multi-port bridge according to claim 15 wherein the destination port receives the data packet from the source port simultaneously as the source port stores in the data packet in the memory device.

17. The multi-port bridge according to claim 12 wherein a source port is configured to access the look-up table via the look-up bus during a look-up operation to identify a destination port identification associated with a destination node address.

18. The multi-port bridge according to claim 17 wherein the multi-port bridge is configured to transmit a first information packet to the source port in response to the look-up operation initiated by the source port.

19. The multi-port bridge according to claim 18 wherein the multi-port bridge is configured to transmit a second information packet to the destination port in response to the look-up operation initiated by the source port.

20. The multi-port bridge according to claim 19 wherein the second information packet comprises a triplet, and wherein the destination port is configured to store the second information packet in a ready-to-receive queue.

21. A method of transferring data between ports of a multi-port bridge, the method comprising steps of:

a. receiving a first data packet into a source port for the first data packet;

b. conditioning a multiplexer to provide a first signal path from the source port to a memory device, wherein the first signal path is common to the first plurality of ports including the source port;

c. transferring the first data packet from the source port to the memory device;

d. conditioning the multiplexer to provide a second signal path from the memory device to a destination port for the first data packet, wherein the second signal path is common to a second plurality of ports including the destination port; and

e. transferring the first data packet from the memory device to the destination port.

22. The method according to claim 21 further comprising a step of identifying a destination port for the first data packet wherein the step of identifying the destination port for the first data packet comprises a step of communicating a destination address for the first data packet to a look-up table via a look-up bus.

23. The method according to claim 22 further comprising a step of notifying the destination port of its status as a destination port for the first data packet via the look-up bus.

24. The method according to claim 21 further comprising steps of:

a. receiving a second data packet into a source port for the second data packet wherein the source port for the first data packet is included in the ports coupled to the first data bus segment; and

b. transferring the second data packet to a destination port for the second data packet wherein the destination port for the second data packet is also included in the ports coupled to the first data bus segment wherein the step of transferring is performed via the first data bus segment.

25. The method according to claim 21 further comprising a step of requesting access to the memory device by the source port.

26. The method according claim 25 further comprising a step of granting access to the memory device wherein the step of granting access is performed in response to the step of requesting access and wherein the step of transferring the first data packet to the memory device is performed in response to the step of granting access.