Interface and process for handling out-of-order data transactions and synchronizing events in a split-bus system

• US 6,363,466 B1
• Filed: 09/13/1999
• Issued: 03/26/2002
• Est. Priority Date: 09/13/1999
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Anand, Vishal
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US09/394,395
• Time in Patent Office: 925 Days
• Field of Search: 711/151, 711/158, 711/169, 710/112
• US Class Current: 711/169
• CPC Class Codes: G06F 13/1626 by reordering requests

Abstract

An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In such an interface where data transactions can be in any order, certain events may occur that force the reordering to be limited to either before or after the event. These events, also referred to as synchronizing events herein, require that transactions sampled before the event must be completed before transactions sampled after the event are completed. The present invention is capable of handling such synchronizing events while maximizing reordering to gain maximum performance benefits.

Claims

1. In a computer system, a method of processing memory access requests generated by a master device, said method comprising the steps of:

a) receiving a first plurality of memory access requests generated by said master device;

b) upon receiving a first synchronizing request from said master device, presenting a first plurality of memory access requests to a memory access request arbiter in parallel for re-ordering thereof;

c) receiving a second plurality of memory access requests generated by said master device when said first plurality of memory access requests are serviced by said memory access request arbiter;

d) processing said first synchronizing request after said first plurality of memory access requests have been completed; and

e) upon receiving a second synchronizing request from said master device, presenting said second plurality of memory access requests to said memory access request arbiter in parallel for re-ordering thereof.

2. A method as recited in claim 1 wherein said step (c) comprises the step of appending an identifier to a respective one of said second plurality of memory access requests wherein said identifier indicates a storage location of said first synchronizing request.

3. A method as recited in claim 2 wherein said step (a) further comprises the step of appending said identifier to a second synchronizing request that follows said set of memory access requests.

4. A method as recited in claim 2 wherein said step (b) comprises the step of monitoring said storage location to determine whether said first synchronizing request has been processed.

5. A method as recited in claim 1 wherein step (d) further comprises the step of monitoring storage locations of said first plurality of memory access requests to determine whether said first plurality of memory access requests have been completed.

6. A method as recited in claim 1 wherein said step (b) comprises the step of presenting said set of memory access requests to a memory access request arbiter for re-ordering thereof.

7. A method as recited in claim 1 wherein said master device comprises a central-processing unit (CPU).

8. A computer system comprising:

a processor;

a first bus coupled to said processor;

a memory controller coupled to said processor via said first bus;

a memory coupled to said memory controller via a second bus;

wherein said memory controller further comprises;

a memory access request arbiter for re-ordering memory access requests;

a buffer that has a plurality of storage locations for storing memory access requests and synchronizing requests; and

a request selection unit that causes said buffer to present a first plurality of memory access requests in parallel to said memory access request arbiter upon receiving a first synchronizing request without stalling said processor.

9. A computer system as recited in claim 8 wherein said memory controller continues to receive a second plurality of memory access requests generated by said processor while said first plurality of memory access requests are serviced by said memory.

10. A computer system as recited in claim 9 wherein said request selection unit appends an identifier to each of said second plurality of memory access requests wherein said identifier indicates a storage location of said first synchronizing request.

11. A computer system as recited in claim 10 wherein said request selection unit determines whether said second plurality of memory access requests are ready to be serviced by said memory by monitoring said storage location of said first synchronizing request.

12. A computer system as recited in claim 10 wherein said request selection unit determines whether said first synchronizing request is ready to be processed by monitoring storage locations of said first plurality of memory access requests.

13. A memory controller as recited in claim 10 wherein said request selection unit determines whether said second plurality of memory access requests are ready to be serviced by said memory by monitoring said storage location of said first synchronizing request.

14. A memory controller as recited in claim 10 wherein said request selection unit determines whether said first synchronizing request is ready to be processed by monitoring storage locations of said first plurality of memory access requests.

15. A computer system as recited in claim 9 wherein said request selection unit causes said buffer to present said second plurality of memory access requests in parallel to said memory access request arbiter upon receiving a second plurality of memory access requests without stalling said processor.

16. A computer system as recited in claim 15 wherein said request selection unit appends an identifier to said second synchronizing request wherein said identifier indicates a storage location of said first synchronizing request.

17. A computer system as recited in claim 16 wherein said memory controller determines whether said second synchronizing request is ready to be processed by monitoring said storage location of said first synchronizing request and storage locations of said first plurality of memory access requests.

18. A memory controller as recited in claim 16 wherein said memory controller determines whether said second synchronizing request is ready to be processed by monitoring said storage location of said first synchronizing request and storage locations of said first plurality of memory access requests.

19. A memory controller as recited in claim 15 wherein said request selection unit appends an identifier to said second synchronizing request wherein said identifier indicates a storage location of said first synchronizing request.

20. A memory controller as recited in claim 9 wherein said request selection unit appends an identifier to each of said second plurality of memory access requests wherein said identifier indicates a storage location of said first synchronizing request.

21. A memory controller as recited in claim 9 wherein said request selection unit causes said buffer to present said second plurality of memory access requests in parallel to said memory access request arbiter upon receiving a second plurality of memory access requests without stalling said processor.

22. A memory controller as recited in claim 8 wherein said memory controller continues to receive a second plurality of memory access requests generated by said processor while said first plurality of memory access requests are serviced by said memory.

23. A memory controller comprising:

an input for coupling to a master device and for receiving memory access requests generated by said master device;

a memory access request arbiter for re-ordering memory access requests generated by said master device;

a buffer that has a plurality of storage locations for storing memory access requests and synchronizing requests generated by said master device; and

a request selection unit that causes said buffer to present a first plurality of memory access requests in parallel to said memory access request arbiter upon receiving a first synchronizing request without stalling said processor.