Smart column controls for high speed multi-resolution sensors

• US 6,365,886 B1
• Filed: 02/18/1999
• Issued: 04/02/2002
• Est. Priority Date: 02/18/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Photobit Corporation (Micron Technology, Inc.)
• Inventors: Krymski, Alexander I., Ang, Lin Ping
• Primary Examiner(s): EVANS, FANNIE L
• Application Number:
  US09/251,758
• Time in Patent Office: 1,139 Days
• Field of Search: 250/208.1, 250/214.A, 348/308, 348/302, 348/294, 358/482, 358/483
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/445 by skipping some contiguous pixels within the read portion of the array
• CPC Class Codes: H04N 25/701 Line sensors
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers

Abstract

Smarts are added to a CMOS active pixel color linear image sensor operable in any of parallel-packed, pixel-packed, and line-packed readout mode, to provide the added feature of variable imaging resolution operability. By combining decoder block functionality with shift selection logic to provide column selection adaptable for lowering the resolution of an imaging process, higher speed imaging is possible. Furthermore, the added functionality is implemented in a manner which does not unduly impact chip size. More importantly, the added functionality is compatible with, and in fact complements the specific architecture of an active pixel color linear sensor with variable readout mode functionality incorporated therein.

Claims

1. A single-chip active pixel sensor operable in at least a first and second resolution mode comprising:

at least first and second line arrays defined by a plurality of pixel storage elements, each storage element causing a current pixel value stored therein to be readout in response to at least a corresponding column address signal; and

column selection logic including a plurality of decoder blocks coupled to a plurality of shift registers, the column selection logic generating a first number of column address signals for reading out a first subset of the storage elements when in the first resolution mode, and generating a second number of column address signals for reading out a second subset of the storage elements when in the second resolution mode,

wherein non-selected storage elements are not read out, and

wherein the first and second subset include storage elements from all the line arrays.

2. The sensor of claim 1, wherein the second subset is a subset of said first subset.

3. The sensor of claim 1, wherein the sensor is a linear sensor.

4. The sensor of claim 3, wherein the sensor is a color linear sensor.

5. The sensor of claim 4, wherein the sensor is a three-color linear image sensor.

6. The sensor of claim 5, further comprising means for sampling data in line-packed mode, and wherein the second subset is a subset of the first subset with the first and second subsets being of the same color pixel elements.

7. The sensor of claim 6, wherein each line array includes at least 5100 storage elements.

8. The sensor of claim 6, wherein the plurality of shift registers is a chain of D flip flops.

9. The sensor of claim 8, wherein the output of each flip flop drives an enable input at an associated one of the plurality of decoder blocks.

10. The sensor of claim 5, wherein each line array includes at least 5100 storage elements.

11. The sensor of claim 1, wherein the sensor is an non-linear or array sensor.

12. The sensor of claim 10, wherein the plurality of shift registers is a chain of D flip flops.

13. The sensor of claim 12, wherein the output of each flip flop drives an enable input at an associated one of the plurality of decoder blocks.

14. An active pixel color linear image sensor operable in at least a first and second resolution mode and selectively operable in at least one of pixel-packed and line-packed pixel readout modes comprising:

first, second and third line arrays each defined by a plurality of pixel storage elements, each storage element causing a current pixel value stored therein to be readout in response to at least a corresponding column address signal; and

column selection logic including a plurality of decoder blocks coupled to a plurality of shift registers, the column selection logic generating a first number of column address signals for reading out a first subset of the storage elements when in the first resolution mode, and generating a second number of column address signals for reading out a second subset of the storage elements when in the second resolution mode,

wherein non-selected storage elements are not read out, and

wherein the first and second subset include storage elements from all three line arrays.

15. The sensor of claim 14, wherein the sensor is on a single-chip.

16. The sensor of claim 15, wherein the plurality of shift registers is a chain of D flip flops.

17. The sensor of claim 16, wherein the output of each flip flop drives an enable input at an associated one of the plurality of decoder blocks.

18. The sensor of claim 14, wherein the plurality of shift registers is a chain of D flip flops.

19. The sensor of claim 18, wherein the output of each flip flop drives an enable input at an associated one of the plurality of decoder blocks.