High speed readout architecture for analog storage arrays

• US 6,366,320 B1
• Filed: 12/08/1997
• Issued: 04/02/2002
• Est. Priority Date: 12/08/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nair, Rajendran, Afghahi, Morteza, Beiley, Mark A.
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US08/987,131
• Time in Patent Office: 1,576 Days
• Field of Search: 348/294, 348/311, 348/312, 348/315, 348/316, 348/317, 348/320, 348/322, 348/241, 348/306, 348/300, 348/308, 378/98.8, 378/98.11
• US Class Current: 348/300
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next. Also, maintaining only two cells active at any given time during readout helps reduce power dissipation and substantially decouples power dissipation in the sense amp array from the size of the array. The embodiments of the invention can be used in different types of imaging systems, including for instance a digital camera.

Claims

1. A method comprising:

sampling outputs of sensor elements in a sensor array one row at a time by performing a)-d) while sampling each row as follows

a) activating a current pair of sense amplifier cells coupled to the sensor array, the current pair having a near cell and a far cell, by causing the current pair to change from a low power consumption state to a high power consumption state; and

then

b) driving at least one signal, which represents an output of a first sensor element in a row of the sensor array, from the near cell of the current pair; and

then

c) activating a subsequent pair of sense amplifier cells coupled to the array, a near cell of the subsequent pair being the far cell of the current pair and a far cell of the subsequent pair being separate from the current pair of cells, by causing the far cell of the subsequent pair to change from a low power consumption state to a high power consumption state; and

then

d) driving at least one signal, which represents an output of a second sensor element in said row from the near cell for the subsequent pair.

2. A method as in claim 1 further comprising deactivating the near cell of the current pair prior to driving the at least one signal from the near cell of the subsequent pair.

3. The method of claim 2 wherein said driving at least one signal from the near cell of the current pair comprises driving a differential signal pair.

4. A method as in claim 1 wherein said activating a current pair of sense amplifier cells comprises applying power to at least one operational amplifier in said current pair.

8. An imaging apparatus as in claim 1 further comprising an operational amplifier (opamp) pair in each CDS cell providing one of the plurality of differential signal pairs, each CDS cell being activated by applying power to the opamp pair in response to any one of the first control signal and the second control signal.

10. An imaging apparatus as in claim 1 further comprising

timing signal generation unit that generates the first and the second signals.

5. An imaging apparatus comprising:

image sensor array having a plurality of bitlines lines, each bitline coupled to a group of photocells in said sensor array, each photocell generating first and second signals on said bitline;

correlated double sampling (CDS) array having a plurality of CDS cells generating a plurality of differential signal pairs, each CDS cell being associated with one of said bitlines and providing one of said differential signal pairs in response to receiving first and second cell signals on its associated bitline, each CDS cell is activated by changing from a low power or power off mode to a high power mode in response to a signal being asserted by the imaging apparatus at either one of first and second control inputs of each cell, each CDS cell drives the associated differential signal pair in response to a signal being asserted at the first control input, but not the second control input;

analog multiplexer having first and second multiplexers (muxes), each mux having a plurality of inputs and one output, the first muxes receiving the differential signal pairs at their inputs, a subset of the first muxes having an associated second mux, the inputs of the associated second mux being coupled to a plurality of outputs of the subset of the first muxes, and control logic for selecting a first mux from the subset and the associated second mux to pass one of said differential signal pairs through the first and second mux and out of said analog multiplexer;

analog to digital converter unit coupled to the analog multiplexer for converting analog signals related to the differential signal pair into digital signals representing raw image data;

means for digital signal and image processing (DSIP), the means generating captured image data in response to receiving the digital signals; and

output interface for transferring the captured image data to an image processing system separate from the imaging apparatus.

6. An imaging apparatus as in claim 5 wherein each CDS cell comprises

a pair of operational amplifiers (opamps) configured as unity gain closed loop amplifiers to drive the first and second signals, respectively, through the analog multiplexer.

7. An imaging apparatus as in claim 6 wherein at least one of said pair of opamps is configured to yield an underdamped response at its output node when driving the first signal through the analog multiplexer.

9. An imaging apparatus as in claim 5 further comprising

system controller for managing the operations of the apparatus in response to instructions stored in firmware.

11. An imaging apparatus as in claim 5 wherein the means for DSIP comprises hardwired logic circuitry.

12. A circuit comprising:

a plurality of amplifier cells, each amplifier cell being coupled to a respective one of a plurality of output lines of an analog storage array and having a signal input and a signal output, the signal input being coupled to said respective one of the output lines, each amplifier cell having first and second control inputs, each amplifier cell changes from a low power or power off mode to a high power mode in response to a control signal received at any one of the first and second control inputs, and drive the signal output in response to a control signal received at the second control input but not the first control input.

13. The circuit of claim 12 further comprising:

an amplifier in series with a switch coupled between the signal input and the signal output in each amplifier cell, the switch being coupled to the second control input and configured to close in response to the control signal received at the second input.

14. The circuit of claim 13 wherein the amplifier in each amplifier cell has a power supply input coupled to the first control input for being turned on in response to the control signal received at the first input.

15. The circuit of claim 12 wherein the signal output of each amplifier cell has dual lines to provide a differential output signal pair.

16. The circuit of claim 12 wherein the analog storage array includes photosensitive cells forming an image sensor array.

17. The circuit of claim 16 wherein the amplifier cells and the image sensor array are formed in the same integrated circuit die.

18. The circuit of claim 17 wherein the die is fabricated by a MOS process.

19. In an electronic system having a sensor array with a plurality of bitlines that are coupled to a plurality of amplifier cells, each cell being coupled to a respective bitline, a method for sampling outputs of sensor elements in the array, comprising:

activating each one of the plurality of amplifier cells sequentially one pair at a time, by causing each pair to change from a low power mode to a high power mode, each pair having a near cell and a far cell, the near cell of a pair being the same as the far cell of an adjacent pair; and

while each pair is in the high power mode, driving a signal that represents an output of a separate sensor element in the array from the near cell and not the far cell of each pair.