Method of fabricating an antifuse element

• US 6,368,900 B1
• Filed: 02/11/2000
• Issued: 04/09/2002
• Est. Priority Date: 02/11/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Xiang, Qi Dong, Kenkaraseril, John Prasao, Teo, Yeow-Meng, Mukhopadhyay, Madhusudan
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/501,374
• Time in Patent Office: 788 Days
• Field of Search: 438/631, 438/634, 438/637, 438/131
• US Class Current: 438/131
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for forming an amorphous silicon, antifuse element, on an underlying, raised tungsten plug structure, has been developed. The process features the recessing of the insulator layer, in which the tungsten plug structure resides, resulting in a raised portion of a tungsten plug structure. Conductive spacers are then formed on the exposed sides of the raised portion of the tungsten plug structure, resulting in smooth edges, at the perophery of the raised tungsten plug structure. An amorphous silicon layer is then deposited and defined to create the amorphous silicon, antifuse element, on the underlying raised tungsten plug structure, smoothed via the addition of the conductive, sidewall spacers. The use of the underlying, smooth, raised tungsten plug structure, alleviates excessive current crowding, presnet at the edges of the raised tungsten plug structure, during a high voltage pulsing procedure, performed to the overlying antifuse element.

Claims

1. A method of forming an antifuse element, on a semiconductor substrate, comprising the steps of:

providing a conductive region, comprised with a body of gate array devices;

forming a via hole, in a first insulator layer, exposing a portion of said conductive region;

forming a metal plug structure, comprised with a smooth top surface, in said via hole;

removing a top portion of said first insulator layer, resulting in a raised portion of said metal plug structure, protruding upward from the top surface of the etched back, insulator layer;

forming conductive spacers only on the sides of said raised portion of said metal plug structure;

depositing an amorphous silicon layer, overlying said smooth top surface of said metal structure;

depositing a titanium nitride layer on said amorphous silicon layer; and

patterning of said titanium nitride layer, and of said amorphous silicon layer to form said antifuse element, comprised of said amorphous silicon layer, located underlying said titanium nitride layer.

2. The method of claim 1, wherein said first insulator layer is either comprised of silicon oxide, or borophosphosilicate glass, obtained via LPCVD or PECVD procedures, at a thickness between about 5000 to 15000 Angstroms.

3. The method of claim 1, wherein said via hole, in said insulator layer, is formed via a RIE procedure, using CHF₃ as an etchant.

4. The method of claim 1, wherein said metal plug structure is a tungsten plug structure, formed from a tungsten layer which is obtained via CVD, or PVD procedures, at a thickness between about 4000 to 8000 Angstroms.

5. The method of claim 1, wherein said metal plug structure is formed in said via hole via removal of regions of a metal layer, from the top surface of said insulator layer, via a chemical mechanical polishing procedure.

6. The method of claim 1, wherein said top portion of said insulator layer, at a thickness between about 200 to 1000 Angstroms, is removed via a selective wet etch procedure, using a buffered hydrofluoric acid solution.

7. The method of claim 1, wherein said conductive spacers, on the sides of said raised portion of said metal plug structure, is comprised of an underlying layer of titanium nitride, obtained via PVD, or CVD procedures, at a thickness between about 100 to 500 Angstroms, and comprised of an overlying layer of tungsten, obtained via CVD, or PVD procedures, at a thickness between about 400 to 2000 Angstroms.

8. The method of claim 1, wherein said conductive spacers are formed on the sides of said raised portion of said metal plug structure, via an anisotropic RIE procedure, using Cl₂ or SF₆ as an etchant.

9. The method of claim 1, wherein said amorphous silicon layer is obtained via LPCVD procedures, at a temperature between about 200 to 400°

C., to a thickness between about 200 to 1500 Angstroms.

10. The method of claim 1, wherein said titanium nitride layer is obtained via PVD procedures, to a thickness between about 1000 to 2000 Angstroms.

11. A method of forming an amorphous silicon, antifuse element, overlying a raised tungsten plug structure, featuring conductive composite spacers formed on the sides of the raised portion of the tungsten plug structure;

comprising the steps of;

providing a conductive region, comprised with a body of gate array devices;

depositing a silicon oxide layer;

opening a via hole in said silicon oxide layer, exposing a portion of a conductive component in said body of gate array devices;

depositing a first tungsten layer, completely filling said via hole;

removing regions of said first tungsten layer from the top surface of said silicon oxide layer, creating a tungsten plug structure, in said via hole, and with said tungsten plug structure comprised with sharp corners at the top perimeter of said via hole and comprised with a smooth top surface;

performing a selective wet etch to recess said silicon oxide layer, resulting in said raised tungsten plug structure, with a top portion of said raised tungsten plug structure protruding upward from the top surface the recessed silicon oxide layer;

depositing a first titanium nitride layer;

depositing a tungsten layer;

performing an anisotropic reactive ion etching procedure to form conductive composite spacers, comprised of underlying said first titanium nitride layer, and of overlying tungsten layer, on the sides of said top portion of said raised tungsten plug structure, via removal of said first titanium nitride layer and said tungsten layer from said smooth top surface of said raised tungsten plug structure;

depositing an amorphous silicon layer, directly overlying said smooth top surface of said raised tungsten plug structure, and overlying said conductive composite spacers;

depositing a second titanium nitride layer;

patterning of said second titanium nitride layer, and of said amorphous silicon layer, to form said antifuse element, comprised of said amorphous silicon, underlying said second titanium nitride layer, with said antifuse element overlying said smooth top surface of said raised tungsten plug structure, and overlying said composite spacers; and

performing a clean procedure to said antifuse element, via use of a wet developer solution.

12. The method of claim 11, wherein said silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 5000 to 15000 Angstroms.

13. The method of claim 11, wherein said via hole, in said silicon oxide layer, is formed via a RIE procedure, using CHF₃ as an etchant.

14. The method of claim 11, wherein said first tungsten layer is obtained via CVD, or PVD procedures, at a thickness between about 4000 to 8000 Angstroms.

15. The method of claim 11, wherein said tungsten plug structure is formed in said via hole, via removal of regions of said tungsten layer, from the top surface of said silicon oxide layer, via a chemical mechanical polishing procedure.

16. The method of claim 11, wherein said selective wet etch procedure, used to remove a top portion of said silicon oxide layer, is performed using a buffered hydrofluoric acid solution.

17. The method of claim 11, wherein said top portion of said silicon oxide, removed via said selective wet etch procedure, is between about 200 to 1000 Angstroms.

18. The method of claim 11, wherein said conductive composite spacers are comprised with underlying, said first titanium nitride layer obtained via PVD, or CVD procedures, at a thickness between about 100 to 500 Angstroms.

19. The method of claim 11, wherein said conductive composite spacers are comprised with overlying said tungsten layer, obtained via CVD, or via PVD procedures, at a thickness between about 400 to 2000 Angstroms.

20. The method of claim 11, wherein said conductive composite spacers are formed via an anisotropic RIE procedure, using Cl₂ or SF₆ as an etchant for second tungsten layer and for first titanium nitride layer.

21. The method of claim 11, wherein said amorphous silicon layer is obtained via LPCVD procedures, at a temperature between about 200 to 400°

C., to a thickness between about 200 to 1500 Angstroms.

22. The method of claim 11, wherein said second titanium nitride layer is obtained via PVD procedures, to a thickness between about 1000 to 2000 Angstroms.

23. The method of claim 11, wherein said antifuse element, comprised of said amorphous silicon layer, underlying said second titanium nitride layer, is defined via a selective RIE procedure, using Cl₂ or SF₆ as an etchant.