Configurable universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip with media access control (MAC)

• US 6,370,603 B1
• Filed: 10/05/1998
• Issued: 04/09/2002
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Inventors: Silverman, Joel, Rostoker, Michael D.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US09/166,501
• Time in Patent Office: 1,282 Days
• Field of Search: 710/56, 710/72, 710/62, 710/63, 710/126, 710/129, 709/220
• US Class Current: 710/72
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An interface device is provided which enables communications between devices having disparate protocols (e.g., USB and Ethernet), and can be fabricated on a single integrated circuit (IC) chip. A system incorporating the interface device provides plug-and-play capability for both MAC and nonMAC environments. A “smart” cable incorporating the interface device has the ability to recognize what type of external device using what type of protocol is connected to the “other” end of the cable, thereby enabling a host to communicate with the external device. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Claims

1. A universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip, for interfacing to peripheral devices with alternative protocol matching, comprising:

a USB transceiver;

a serial interface engine (SIE) in communication with the USB transceiver; and

a user-programmable section in communication over a connection with the SIE and programmable by the user with standard tools.

2. A universal serial bus (USB) controller, according to claim 1, wherein:

the user-programmable section comprises programmable logic devices (PLD).

3. A universal serial bus (USB) controller, according to claim 1, wherein:

the user-programmable section comprises a field-programmable gate array (FPGA).

4. A universal serial bus (USB) controller, according to claim 1, wherein:

the user-programmable section comprises 5K gates.

5. A universal serial bus (USB) controller, according to claim 1, further comprising:

a phase lock loop (PLL) and clock generator operatively connected with the serial interface engine (SIE);

a processor section operatively connected with the serial interface engine, with the user-programmable section, and with the phase lock loop (PLL) and clock generator;

read-only memory (ROM) for storing a user'"'"'s software instructions for running the processor; and

random access memory (RAM) operatively connected to the processor.

6. A universal serial bus (USB) controller, according to claim 5, wherein:

the read-only memory (ROM) is selected from the group consisting of Flash memory and Mask ROM.

19. A universal serial bus (USB) controller, according to claim 1, further comprising:

read-only memory (ROM) in communication with the user-programmable section.

20. A universal serial bus (USB) controller, according to claim 19, wherein the user-programmable section comprises one of programmable logic device (PLD) and a field-programmable gate array (FPGA).

21. A universal serial bus (USB) controller, according to claim 19, further comprising:

a processor section operatively connected with the serial interface engine.

22. A universal serial bus (USB) controller, according to claim 1, further comprising:

a general purpose I/O (GPIO) circuit.

29. A universal serial bus (USB) controller, according to claim 1, further comprising:

a processor in communication over a second connection with the SIE and the user-programmable section.

30. A universal serial bus (USB) controller, according to claim 29, wherein:

the second connection comprises a bus shared with other components.

31. A universal serial bus (USB) controller, according to claim 1, wherein:

the connection comprises a dedicated connection.

32. A universal serial bus (USB) controller, according to claim 1, wherein:

the connection comprises a bus shared with other components.

7. An electronic system incorporating at least one integrated circuit (IC chip), said IC chip comprising:

a USB transceiver;

a serial interface engine (SIE) in communication with the USB transceiver; and

a user-programmable section in communication over a connection with the SIE and programmable by the user with standard tools.

8. An electronic system, according to claim 7, wherein:

the user-programmable section comprises programmable logic devices (PLD).

9. An electronic system, according to claim 7, wherein:

the user-programmable section comprises a field-programmable gate array (FPGA).

10. An electronic system, according to claim 7, wherein:

the user-programmable section comprises 5K gates.

11. An electronic system, according to claim 7, further comprising:

a phase lock loop (PLL) and clock generator operatively connected with the serial interface engine (SIE);

a processor section operatively connected with the serial interface engine, with the user-programmable section, and with the phase lock loop (PLL) and clock generator;

read-only memory (ROM) for storing a user'"'"'s software instructions for running the processor; and

random access memory (RAM) operatively connected to the processor.

12. An electronic system, according to claim 11, wherein:

the read-only memory (ROM) is selected from the group consisting of Flash memory and Mask ROM.

13. An electronic system, according to claim 7, wherein the electronic system is selected from the group consisting of general-purpose computer, telecommunication device, network device, consumer device, receiver, recorder, display device, and vehicle.

18. An electronic system, according to claim 7, wherein said IC chip further comprises:

a general purpose I/O (GPIO) circuit.

27. An electronic system, according to claim 7, wherein:

the connection comprises a dedicated connection.

28. An electronic system, according to claim 7, wherein:

the connection comprises a bus shared with other components.

14. A universal serial bus (USB) controller for interfacing to peripheral devices with alternative protocol matching, comprising:

a USB transceiver;

a serial interface engine (SIE) in communication with the USB transceiver;

a user-programmable section in communication over a connection with the SIE and programmable by the user with standard tools; and

read-only memory (ROM) in communication with the user-programmable section,

wherein the USB controller is implemented either on a single board, multichip module, or a single integrated circuit (IC) chip.

15. A universal serial bus (USB) controller, according to claim 14, wherein the user-programmable section comprises one of programmable logic device (PLD) and a field-programmable gate array (FPGA).

16. A universal serial bus (USB) controller, according to claim 14, further comprising:

a processor section operatively connected with the serial interface engine.

17. A universal serial bus (USB) controller, according to claim 14, further comprising:

a general purpose I/O (GPIO) circuit.

23. A universal serial bus (USB) controller, according to claim 14, further comprising:

a processor in communication over a second connection with the SIE and the user-programmable section.

24. A universal serial bus (USB) controller, according to claim 23, wherein:

the second connection comprises a bus shared with other components.

25. A universal serial bus (USB) controller, according to claim 14, wherein:

the connection comprises a dedicated connection.

26. A universal serial bus (USB) controller, according to claim 14, wherein:

the connection comprises a bus shared with other components.