Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria
First Claim
1. A method for allocating a plurality of instructions to a plurality of execution pipelines, the method comprising:
- receiving the plurality of instructions, wherein one or more of the plurality of instructions are multi-pipeline executable, wherein the remaining instructions are single-pipeline executable, wherein the multi-pipeline executable instructions are capable of being executed by more than one type of execution pipeline, and wherein the single-pipeline executable instructions are executable by only one type of execution pipeline;
allocating each single-pipeline executable instruction to one of the plurality of execution pipelines according to instruction type; and
allocating each multi-pipeline executable instruction to one of the plurality of execution pipelines according to a set of criteria, wherein the set of criteria includes determining whether at least one other multi-pipeline executable instruction is present in the plurality of instructions.
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Accused Products
Abstract
A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point unit'"'"'s pipeline (e.g., during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessor'"'"'s execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.
16 Citations
20 Claims
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1. A method for allocating a plurality of instructions to a plurality of execution pipelines, the method comprising:
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receiving the plurality of instructions, wherein one or more of the plurality of instructions are multi-pipeline executable, wherein the remaining instructions are single-pipeline executable, wherein the multi-pipeline executable instructions are capable of being executed by more than one type of execution pipeline, and wherein the single-pipeline executable instructions are executable by only one type of execution pipeline;
allocating each single-pipeline executable instruction to one of the plurality of execution pipelines according to instruction type; and
allocating each multi-pipeline executable instruction to one of the plurality of execution pipelines according to a set of criteria, wherein the set of criteria includes determining whether at least one other multi-pipeline executable instruction is present in the plurality of instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for allocating a plurality of instructions to a plurality of execution pipelines, wherein the plurality of execution pipelines comprises at least one addition pipeline, at least one multiplication pipeline, and at least one store pipeline, the method comprising:
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receiving the plurality of instructions, wherein one or more of the plurality of instructions are junk ops; and
allocating each of the plurality of instructions that are not junk ops according to instruction type; and
allocating each of the plurality of instructions that are junk ops to maximize compliance with at least the following criteria;
(i) the one or more store pipelines receive on average as many junk ops as the one or more addition pipelines and one or more multiplication pipelines combined.- View Dependent Claims (11, 12, 13)
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14. A microprocessor comprising:
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an instruction cache configured to store integer instructions and floating point instructions; and
a floating point unit configured to receive the floating point instructions from the instruction cache, wherein the floating point unit comprises;
a plurality of execution pipelines; and
a rename unit configured to allocate the floating point instructions received by the floating point unit to the execution pipelines, wherein the floating point instructions include single pipeline executable instructions that are executable by a particular type of execution pipeline and multi-pipeline executable instructions that are executable by more than one particular type of execution pipeline, wherein the rename unit is configured to allocate multi-pipeline executable instructions substantially in accordance with at least the following criteria;
(i) the execution pipelines configured to execute store instructions receive on average as many multi-pipeline executable instructions as the execution pipelines configured to execute add and multiply instructions combined. - View Dependent Claims (15, 16, 17)
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18. A computer system comprising:
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a main memory;
a communications device; and
a microprocessor coupled to the main memory and the communications device, wherein the microprocessor comprises;
an instruction cache configured to store floating point instructions and integer instructions; and
a floating point unit coupled to receive the floating point instructions from the instruction cache, wherein the floating point unit comprises;
a plurality of execution pipelines; and
a rename unit configured to allocate the floating point instructions received by the floating point unit to the execution pipelines, wherein the floating point instructions include single pipeline executable instructions that are executable by a particular type of execution pipeline and multi-pipeline executable instructions that are executable by more than one particular type of execution pipeline, wherein the rename unit is configured to allocate multi-pipeline executable instructions substantially in accordance with at least the following criteria;
(i) the execution pipelines configured to execute store instructions receive on average as many multi-pipeline executable instructions as the execution pipelines configured to execute add and multiply instructions combined. - View Dependent Claims (19)
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20. A computer software program embodied on a computer-readable media, wherein the program comprises a plurality of instructions, wherein the plurality of instructions are configured to:
allocate a plurality of instructions to a plurality of execution pipelines, wherein the plurality of execution pipelines comprises at least one addition pipeline, at least one multiplication pipeline, and at least one store pipeline, wherein the instructions are configured to allocate each of the plurality of instructions that are non-multi-pipeline executable according to instruction type and each of the plurality of instructions that are multi-pipeline executable according to at least the following criteria;
(i) the one or more store pipelines receive on average as many multi-pipeline executable instructions as the one or more addition pipelines and one or more multiplication pipelines combined; and
(ii) if there are more stores than the number of store pipelines, no multi-pipeline executable instructions are sent to the one or more store pipelines.
Specification