Method of making a TFT array with photo-imageable insulating layer over address lines

• US 6,372,534 B1
• Filed: 04/12/1996
• Issued: 04/16/2002
• Est. Priority Date: 06/06/1995
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: den Boer, Willem, Zhong, John Z. Z., Gu, Tieer
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/630,984
• Time in Patent Office: 2,195 Days
• Field of Search: 438/30, 438/29, 438/155, 438/FOR.51, 257/59, 257/57
• US Class Current: 438/30
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/42 Materials having a particular dielectric constant
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.

Claims

1. A method of making a thin film transistor (TFT) array including a first substrate, comprising:

forming a plurality of TFT gate electrodes connected to gate lines on the first substrate;

forming a gate insulating layer over the gate electrodes;

forming a semiconductor layer over each of the gate electrodes in TFT areas;

forming TFT source and drain electrodes in each TFT area with a TFT channel therebetween and a plurality of corresponding drain lines, thereby forming an array of TFTs on the first substrate;

depositing a photo-imageable insulating layer having a dielectric constant less than about 5.0 over a substantial portion of the substrate so as to cover substantial portions of the gate and drain lines and the TFTs in the array;

photo-imaging the insulating layer so as to form a plurality of vias therein, at least one via corresponding to each TFT in the array;

forming a plurality of pixel electrodes over the insulating layer so that each pixel electrode is in communication with the source electrode of a corresponding TFT through one of the vias; and

forming the pixel electrodes on the substrate so that each pixel electrode overlaps one of the drain and gate line whereby the pixel electrodes are insulated from the lines in the overlap areas by the photo-imaged insulating layer,

wherein the parasitic capacitance corresponding to an overlap of said each pixel electrode to one of the drain and gate lines is no greater than 0.01 pF.

2. The method of claim 1, wherein the photo-imageable insulating layer has a dielectric constant of less than about 3.0 over a substantial portion of the substrate.

3. The method of claim 1, wherein the photo-imageable insulating layer has a thickness of about 1.5 μ

m in areas where the pixel electrode overlaps one of the drain and gate lines.

4. The method of claim 1, wherein the pixel pitch of the display is about 150 μ

m.

5. A method of making a liquid crystal display including an array of thin film transistors (TFTs), comprising:

providing a first substrate;

forming an array of semiconductor based TFTs and corresponding address lines on the first substrate;

forming an organic insulating layer on the first substrate over the TFTs and address lines, the organic insulating layer having a dielectric constant of less than about 5.0;

photo-imaging the insulating layer to forming a plurality of contact holes therein; and

forming an array of pixel electrodes over the photo-imaged insulating layer so that each pixel electrode communicates with one of the TFTs through a corresponding one of the contact holes in the insulating layer,

wherein the pixel electrodes overlap at least one of the address lines thereby resulting in a high aperture display which includes a pixel aperture ratio greater than a display without such overlap and a parasitic capacitance corresponding to an overlap of one of the pixel electrodes to one of the drain and gate lines is no greater than 0.01 pF.

6. The method of claim 5, wherein the organic insulating layer has a dielectric constant of less than about 3.0.

7. The method of claim 5, wherein the organic insulating layer is from about 1.0 to 2.5 μ

m thick.

8. The method of claim 7, wherein the insulating layer is substantially transparent.

9. A method of making a liquid crystal display having a substrate including an array of transistors, comprising:

forming an array of transistors and corresponding address lines on the substrate;

forming an organic insulating layer on the substrate over the transistors and address lines, the organic insulating layer having a dielectric constant of less than about 5.0 and a thickness in areas thereof of at least about 1.0 μ

m;

photo-imaging the organic insulating layer to form a plurality of contact holes therein;

forming a plurality of pixel electrodes over the photoimaged organic insulating layer so that each pixel electrode overlaps at least a portion of at least one of the address lines and communicates with one of the transistors through a corresponding one of the contact holes in the organic insulating layer; and

providing the organic insulating layer in a thickness of at least about 1.0 μ

m in areas thereof so that the line-pixel capacitance between at least one address line and an overlapping pixel electrode sandwiching the organic insulating layer therebetween is less than about 20 fF.

10. The method of claim 9, wherein the organic insulating layer has a dielectric constant of less than about 3.0 over a substantial portion of the substrate.

11. The method of claim 9, wherein the organic insulating layer has a thickness of about 1.5 μ

m in areas where the pixel electrode overlaps one of the address lines.

12. The method of claim 9, wherein the line-pixel capacitance is less than or equal to 12 fF.