Copper interconnect for an integrated circuit and methods for its fabrication

• US 6,373,137 B1
• Filed: 03/21/2000
• Issued: 04/16/2002
• Est. Priority Date: 03/21/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: McTeer, Allen
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/532,087
• Time in Patent Office: 756 Days
• Field of Search: 257/762, 257/763, 257/764, 257/765
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/0101 Neon [Ne]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A multi layered copper bond pad for a semiconductor die which inhibits formation of copper oxide is disclosed. A small dose of titanium is implanted in the copper surface. The implanted titanium layer suppresses the copper oxide growth in the copper bond pad by controlling the concentration of vacancies available to the copper ion transport. An interconnect structure such as a wire bond or a solder ball may be attached to the copper-boron layer to connect the semiconductor die to a lead frame or circuit support structure. In another embodiment, a titanium-aluminum passivation layer for copper surfaces is also disclosed. The titanium-aluminum layer is annealed to form a titanium-aluminum-copper alloy. The anneal may be done in a nitrogen environment to form a titanium-aluminum-copper-nitrogen alloy.

Claims

1. An interconnect structure for a semiconductor die, said interconnect structure comprising:

a conductive bond pad containing a copper layer; and

an implant region on at least an upper surface portion of said copper layer, said implant region containing titanium.

2. The interconnect structure of claim 1, wherein said implant region containing titanium has a thickness not greater than 1000 Å

.

3. The interconnect structure of claim 1, wherein said copper layer is elemental copper.

4. The interconnect structure of claim 1, wherein said copper layer contains a thin copper oxide layer thereon.

5. The interconnect structure of claim 4, wherein said copper oxide layer has a thickness not greater than 300 Å

.

6. The interconnect structure of claim 1, further comprising an electrical conductor bonded to said implant region containing titanium.

7. A chip interconnect bond comprising:

a conductive bond pad containing a copper layer;

an implant region on at least an upper surface portion of said copper layer, said implant region containing titanium; and

an electrically conductive bump bonded to said implant region containing titanium.

8. The interconnect bond of claim 7, wherein said implant region containing titanium has a thickness not greater than 1000 Å

.

9. The interconnect bond of claim 7, wherein said implant region containing titanium is approximately 50 Å

to 200 Å

thick.

10. The interconnect bond of claim 7, wherein said conductive bump is a solder ball.

11. The interconnect bond of claim 7, further comprising a circuit substrate bonded to said electrically conductive bump.

12. An integrated circuit comprising:

a semiconductor die having integrated circuitry formed on a substrate;

a conductive bond pad on a surface of said die and in electrical connection with said die integrated circuitry, said conductive bond pad having a copper layer;

an implant region on at least an upper surface portion of said copper layer, said implant region containing titanium;

an electrical conductor bonded to said implant region containing titanium; and

a circuit substrate having a bonding site, wherein said electrical conductor of said semiconductor die is bonded to said bonding site.

13. The integrated circuit of claim 12, wherein said implant region containing titanium is approximately 50 Å

to 200 Å

thick.

14. The integrated circuit of claim 12, wherein said electrical conductor is a wire bond.

15. The integrated circuit of claim 12, wherein said electrical conductor is a tape automated bond.

16. The integrated circuit of claim 12, wherein said electrical conductor is formed as a bump.

17. The integrated circuit of claim 12, wherein said electrical conductor is a conductive adhesive layer.

18. The integrated circuit of claim 12, wherein said electrical conductor is a solder ball.

19. An electronic circuit bonding interconnect structure, said structure comprising:

a bond pad having a copper layer, said copper layer being approximately 500 Å

to 20,000 Å

thick;

an implant region on at least an upper portion of said copper layer, said implant region containing titanium and being approximately 50 Å

to 200 Å

thick; and

an electrical conductor bonded to said titanium layer.

20. The electronic circuit bonding interconnect structure of claim 19, wherein said electrical conductor is a wire bond.

21. The electronic circuit bonding interconnect structure of claim 19, wherein said electrical conductor is a tape automated bond.

22. The electronic circuit bonding interconnect structure of claim 19, wherein said electrical conductor is a conductive adhesive layer.

23. The electronic circuit bonding interconnect structure of claim 19, wherein said electrical conductor is a solder ball.

24. An interconnect structure for a semiconductor die, said interconnect structure comprising:

a conductive bond pad containing a copper layer; and

a titanium-aluminum barrier layer formed over at least an upper surface portion of said copper layer.

25. The interconnect structure of claim 24, wherein said copper layer is elemental copper.

26. The interconnect structure of claim 24, wherein said copper layer contains a thin copper oxide layer thereon.

27. The interconnect structure of claim 26, wherein said copper oxide layer has a thickness not greater than 300 Å

.

28. The interconnect structure of claim 24, wherein said upper surface portion of said copper layer is precleaned.

29. The interconnect structure of claim 24, wherein said titanium-aluminum barrier layer is annealed to form a titanium-aluminum-copper alloy.

30. The interconnect structure of claim 29, wherein said titanium-aluminum-copper alloy is annealed in the presence of nitrogen to form a titanium-aluminum-copper-nitrogen compound.

31. The interconnect structure of claim 24, further comprising an electrical conductor bonded to said titanium-aluminum barrier layer.

32. A chip interconnect bond comprising:

a conductive bond pad containing a copper layer;

a titanium-aluminum barrier layer formed over at least an upper surface portion of said copper layer; and

an electrically conductive bump bonded to said titanium-aluminum barrier layer.

33. The interconnect bond of claim 32, wherein said copper layer is elemental copper.

34. The interconnect bond of claim 32, wherein said copper layer contains a thin copper oxide layer thereon.

35. The interconnect bond of claim 32, wherein said copper oxide layer has a thickness not greater than 300 Å

.

36. The interconnect bond of claim 32, wherein said upper surface portion of said copper layer is precleaned.

37. The interconnect bond of claim 32, wherein said titanium-aluminum barrier layer is approximately 50 Å

to 200 Å

thick.

38. The interconnect bond of claim 32, wherein said titanium-aluminum barrier layer is annealed to form a titanium-aluminum-copper alloy.

39. The interconnect bond of claim 38, wherein said titanium-aluminum-copper alloy is annealed in the presence of nitrogen to form a titanium-aluminum-nitrogen compound.

40. The interconnect bond of claim 32, wherein said electrically conductive bump is a solder ball.

41. The interconnect bond of claim 32, further comprising a circuit substrate bonded to said electrically conductive bump.

42. An integrated circuit comprising:

a semiconductor die having integrated circuitry formed on a substrate;

a conductive bond pad on a surface of said die and in electrical connection with said die integrated circuitry, said conductive bond pad having a copper layer;

a titanium-aluminum layer formed over said copper layer;

an electrical conductor bonded to said titanium-aluminum layer; and

a circuit substrate having a bonding site, wherein said electrical conductor of said semiconductor die is bonded to said bonding site.

43. The integrated circuit of claim 42, wherein said titanium-aluminum layer is approximately 50 Å

to 200 Å

thick.

44. The integrated circuit of claim 42, wherein said electrical conductor is a wire bond.

45. The integrated circuit of claim 42, wherein said electrical conductor is a tape automated bond.

46. The integrated circuit of claim 42, wherein said electrical conductor is formed as a bump.

47. The integrated circuit of claim 42, wherein said electrical conductor is a conductive adhesive layer.

48. The integrated circuit of claim 42, wherein said electrical conductor is a solder ball.

49. The integrated circuit of claim 42, wherein said titanium-aluminum barrier layer is annealed to form a titanium-aluminum-copper alloy.

50. The copper bond pad of claim 49, wherein said titanium-aluminum-copper alloy is annealed in the presence of nitrogen to form a titanium-aluminum-nitrogen compound.