Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

• US 6,376,286 B1
• Filed: 10/20/1999
• Issued: 04/23/2002
• Est. Priority Date: 10/20/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ju, Dong-Hyuk
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): MENZ, LAURA MARY
• Application Number:
  US09/421,305
• Publication Number:
  US 20020025636A1
• Time in Patent Office: 916 Days
• Field of Search: 438/294, 438/411, 438/421, 438/422, 438/243, 438/248, 438/386, 438/391, 438/301, 438/303, 438/433, 438/424, 438/526, 257/66, 257/67, 257/347, 257/349, 257/302, 257/401, 257/329
• US Class Current: 438/149
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Claims

1. A method of forming a field effect transistor on a semiconductor substrate, comprising of:

a) etching an insulating trench around the perimeter of an active region of said transistor to isolate the active region from other structures on said substrate;

b) etching an insulating undercut in the bottom of the insulating trench to isolate at least a portion of the bottom surface of the active region from the substrate; and

c) doping portion of the active region to from each of a source region and a drain region on opposing side of a central channel region, wherein the insulating undercut isolates at least a portion of both the source region and the drain region from the semiconductor substrate, and wherein the undercut isolates at least a portion of the central channel region from the semiconductor substrate, the undercut extending under the central channel region in a direction from the source region to the drain region;

wherein the etching the undercut and the doping from a conductive bridge between the central channel region and the substrate.

2. The method of claim 1 wherein the step of etching the undercut includes the steps of:

a) forming a protective layer on the side walls and bottom of the trench;

b) performing a vertical anisotropic etch of said layer to remove such layer to expose the semiconductor substrate at the bottom of the trench; and

c) performing an isotropic etch of the semiconductor substrate to form said undercut.

3. The method of claim 2 wherein the protective layer is silicon dioxide.

4. The method of claim 2 wherein the isotropic etch is performed using a KOH wet etch.

5. The method of claim 2 wherein the step of forming the insulator includes filling at least a portion of said undercut and said trench using a chemical vapor deposition process using at least one of TEOS or SiH4.

6. The method of claim 1 wherein the conductive bridge has a smaller cross-sectional area than the central channel region.

7. The method of claim 6 wherein the conductive bridge is narrower than the central channel region in every corresponding direction.

8. The method of claim 1 wherein the etching the undercut and the doping form a conductive bridge between the central channel region and the substrate, the conductive bridge having a significantly smaller cross-sectional area than the active region.

9. The method of claim 1, further comprising, prior to the doping, forming a gate on the active region.

10. The method of claim 9 wherein the gate acts as a mask for the doping, thereby defining the central channel region and aligning the source region and the gate region with the gate.

11. The method of claim 1 wherein the etching the insulating trench includes forming a silicon nitride layer, selectively etching the silicon nitride layer, and using the silicon nitride layer as an etch mask for the etching of the insulating trench.

12. The method of claim 2 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut with a depth of between 1,000 and 2,000 Angstroms.

13. The method of claim 12 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut so as to extend under the active portion a distance of between 1,000 and 2,000 Angstroms.

14. A method of forming a field effect transistor on a semiconductor substrate, comprising the steps of:

a) etching an insulating trench around the perimeter of an active region of said transistor to isolate the active region from other structures on said substrate;

b) etching an insulating undercut in the bottom of the insulating trench to isolate at least a portion of the bottom surface of the active region from the substrate, including;

i) forming a protective layer on the side walls and bottom of trench;

ii) performing a vertical anisotropic etch of said layer to remove such layer to expose the semiconductor substrate at the bottom of the trench; and

iii) performing an isotropic etch of the semiconductor substrate to form said undercut;

c) forming a gate on the active region;

d) doping portions of the active region to form each of a source region and a drain region on opposing sides of a central channel region, wherein the gate acts as a mask for the doping, thereby defining the central channel region and aligning the source region and the gate region with the gate, wherein the insulating undercut isolates at least a portion of both the source region and the drain region from the semiconductor substrate, and wherein the undercut isolates at least a portion of the central channel region from the semiconductor substrate, the undercut extending under the central channel region in a direction from the source region to the drain region;

wherein the etching the undercut and the doping form a conductive bridge between the central channel region and the substrate.

15. The method of claim 14 wherein the conductive bridge has a smaller cross-sectional area than the central channel region.

16. The method of claim 15 wherein the conductive bridge is narrower than the central channel region in every corresponding direction.

17. The method of claim 14 wherein the etching the undercut and the doping form a conductive bridge between the central channel region and the substrate, the conductive bridge having a significantly smaller cross-sectional area than the active region.

18. The method of claim 14 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut with a depth of between 1,000 and 2,000 Angstroms.

19. The method of claim 18 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut so as to extend under the active portion a distance of between 1,000 and 2,000 Angstroms.

20. A method of forming a field effect transistor, comprising:

a) etching an insulating trench in a semiconductor substrate to define an active region therein;

b) forming an insulating undercut in the bottom of the insulating trench to isolate a portion of the bottom surface of the active region from a remainder of the substrate, including;

i) forming a protective layer on the side walls and bottom of trench;

ii) performing a vertical anisotropic etch of said layer to remove such layer to expose the semiconductor substrate at the bottom of the trench; and

iii) performing an isotropic etch of the semiconductor substrate to form the undercut;

c) forming a gate on the active region;

d) doping portions of the active region to form each of a source region and a drain region on opposing sides of a central channel region, wherein the gate acts as a mask for the doping, thereby defining the central channel region and aligning the source region and the gate region with the gate, wherein the insulating undercut isolates at least a portion of both the source region and the drain region from the semiconductor substrate, and wherein the undercut isolates at least a portion of the central channel region from the semiconductor substrate, the undercut extending under the central channel region in a direction from the source region to the drain region;

wherein the etching the undercut and the doping form a conductive bridge of semiconductor material between the central channel region and the remainder of the substrate, thereby leaving an electrical connector between the central channel region and the remainder of the substrate via the conductive bridge; and

wherein the conductive bridge has a smaller cross-sectional area than the central channel region.

21. The method of claim 20 wherein the conductive bridge is narrower than the central channel region in every corresponding direction.

22. The method of claim 20 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut with a depth of between 1,000 and 2,000 Angstroms.

23. The method of claim 22 wherein the performing the isotropic etch of the semiconductor substrate includes forming the undercut so as to extend under the active portion a distance of between 1,000 and 2,000 Angstroms.