System having double data transfer rate and intergrated circuit therefor

CAFC
  • US 6,378,020 B2
  • Filed: 04/10/2000
  • Issued: 04/23/2002
  • Est. Priority Date: 04/18/1990
  • Status: Expired due to Fees
First Claim
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1. A system comprising:

  • a first integrated circuit device coupled to an external signal line, the first integrated circuit device including;

    output driver circuitry to output data onto the external signal line wherein;

    the output driver circuitry outputs a first portion of data in response to a rising edge transition of an external clock signal; and

    the output driver circuitry outputs a second portion of data in response to a falling edge transition of the external clock signal; and

    a second integrated circuit device coupled to the external signal line, the second integrated circuit device including;

    output driver circuitry to output data onto the external signal line wherein;

    the output driver circuitry outputs a first portion of data in response to a rising edge transition of the external clock signal; and

    the output driver circuitry outputs a second portion of data in response to a falling edge transition of the external clock signal.

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