Method to form an embedded flash memory circuit with reduced process steps
First Claim
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1. A method of fabricating an embedded FLASH integrated circuit comprising:
- forming a first photoresist film over a semiconductor substrate;
patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; and
partially etching said first region of said polycrystalline silicon film.
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Abstract
A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).
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11 Claims
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1. A method of fabricating an embedded FLASH integrated circuit comprising:
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forming a first photoresist film over a semiconductor substrate;
patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; and
partially etching said first region of said polycrystalline silicon film. - View Dependent Claims (2, 3, 4)
removing said first photoresist film;
forming and patterning a second photoresist film; and
etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.
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5. A method of fabricating an embedded FLASH integrated circuit comprising:
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forming a first photoresist film over a semiconductor substrate;
patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor;
partially etching said first region of said polycrystalline silicon film;
removing said first photoresist film;
forming and patterning a second photoresist film; and
etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor. - View Dependent Claims (6, 7)
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8. A method of simultaneously forming FLASH memory cell gate stacks and NMOS and PMOS gate structures on an embedded integrated circuit comprising:
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forming a first photoresist film over a semiconductor substrate;
patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor;
implanting said first region of said polycrystalline silicon film with a n-type dopant species;
partially etching said first region of said polycrystalline silicon film;
removing said first photoresist film;
forming and patterning a second photoresist film; and
etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor. - View Dependent Claims (9, 10, 11)
a control gate etch comprising a HBr/Cl2/CF4/HeO2 based plasma etch;
a CHF3/O2 based plasma interpoly dielectric etch;
a HBr/Cl2/HeO2 plasma based gate etch; and
a HBr/HeO2 based plasma over etch.
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Specification