CMOS compatible pixel cell that utilizes a gated diode to reset the cell

• US 6,380,571 B1
• Filed: 10/14/1998
• Issued: 04/30/2002
• Est. Priority Date: 10/14/1998
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kalnitsky, Alexander, Bergemont, Albert, Poplevine, Pavel
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): BAUMEISTER, BRADLEY W
• Application Number:
  US09/173,276
• Time in Patent Office: 1,294 Days
• Field of Search: 257/290, 257/291, 257/292, 257/431, 257/443, 257/444-445, 257/461
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14654 Blooming suppression

Abstract

The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.

Claims

1. A pixel cell formed in a semiconductor material of a first conductivity type, the cell comprising:

a first well of a second conductivity type formed in the semiconductor material;

a second well of the first conductivity type formed in the first well;

a gated diode formed in the second well; and

a read out transistor formed in the second well, the read out transistor being spaced apart from the gated diode; and

a cell diode connected between the gated diode and ground.

2. The cell of claim 1 wherein the gated diode includes:

a diffusion region of the second conductivity type formed in the second well;

an inversion region defined in the second well, the inversion region adjoining the diffusion region;

a layer of oxide formed over the inversion region; and

a diode gate formed on the layer of oxide layer.

3. The cell of claim 2 wherein the read out transistor includes:

spaced-apart source and drain regions formed in the second well, the source and drain regions being spaced apart from the diffusion region and the inversion region;

a channel region defined in the second well between the source and drain regions;

a layer of gate oxide formed over the channel region; and

a read out gate formed on the layer of gate oxide over the channel region.

4. The cell of claim 2 wherein the cell diode is connected between the diffusion region and ground.

5. An imaging system formed in a semiconductor material of a first conductivity type, the system comprising:

a pixel cell having;

a first well of a second conductivity type formed in the semiconductor material;

a second well of the first conductivity type formed in the first well;

a gated diode formed in the second well; and

a read out transistor formed in the second well, the read out transistor being spaced apart from the gated diode; and

a cell diode connected between the gated diode and ground; and

a control circuit having;

an oscillator connected to the gated diode;

a counter connected to the gated diode; and

a controller connected to the oscillator, the counter, and the read out transistor.

6. The imaging system of claim 5 wherein the gated diode includes:

a diffusion region of the second conductivity type formed in the second well;

an inversion region defined in the second well, the inversion region adjoining the diffusion region;

a layer of oxide formed over the inversion region; and

a diode gate formed on the layer of oxide layer.

7. The imaging system of claim 6 wherein the read out transistor includes:

spaced-apart source and drain regions formed in the second well, the source and drain regions being spaced apart from the diffusion region and the inversion region;

a channel region defined in the second well between the source and drain regions;

a layer of gate oxide formed over the channel region; and

a read out gate formed on the layer of gate oxide over the channel region.

8. The imaging system of claim 6 wherein the oscillator is connected to the diode gate of the gated diode.

9. The imaging system of claim 6 wherein the counter is connected to the diode gate of the gated diode.

10. The imaging system of claim 6 wherein the cell diode is connected between the diffusion region and ground.

11. The imaging system of claim 5 wherein the oscillator outputs a series of pulses when commanded by the controller, and stops outputting the pulses when commanded by the controller.

12. The imaging system of claim 5 wherein the counter resets a count when commanded by the controller, counts a number of pulses output by the oscillator, and reset the count when commanded by the controller.

13. The imaging system of claim 5 wherein the pixel cell further comprises a select transistor connected to the source region and the controller.

14. The imaging system of claim 5 wherein the pixel cell further comprises:

a variable voltage source; and

a reset transistor connected to the second well and the variable voltage source.

15. A method for operating a pixel cell formed in a semiconductor material of a first conductivity type, the cell comprising:

a first well of a second conductivity type formed in the semiconductor material;

a second well of the first conductivity type formed in the first well;

a gated diode formed in the second well; and

a read out transistor formed in the second well, the read out transistor being spaced apart from the gated diode; and

a cell diode connected between the gated diode and ground,

the method comprising the steps of;

setting a potential on the second well to a first level;

collecting a plurality of photons in the first and second wells, the plurality of photons changing the potential on the second well to a second level; and

applying a number of pulses to the gated diode until the potential on the second well returns to the first level;

counting the number of pulses applied to the gated diode that are required to return the potential on the second well to the first level.

16. The method of claim 15 wherein the gated diode includes:

a diffusion region of the second conductivity type formed in the second well;

an inversion region defined in the second well, the inversion region adjoining the diffusion region;

a layer of oxide formed over the inversion region; and

a diode gate formed on the layer of oxide layer; and

wherein the number of pulses are applied to the diode gate.

17. The method of claim 16 wherein the step of counting pulses is stopped when the current flowing out of the source region is equal to the predefined current after the potential on the second well has changed to the second level.

18. The method of claim 15 wherein the read out transistor includes:

spaced-apart source and drain regions formed in the second well, the source and drain regions being spaced apart from the diffusion region and the inversion region;

a channel region defined in the second well between the source and drain regions;

a layer of gate oxide formed over the channel region; and

a read out gate formed on the layer of gate oxide over the channel region; and

wherein a bias voltage is applied to the drain and read out gate such that a predefined current flows out of the source region when the potential on the second well is at the first level.

19. The method of claim 18 wherein the predefined current is substantially zero.

20. A device comprising:

a semiconductor material of a first conductivity type;

a first well of a second conductivity type formed in the semiconductor material;

a second well of the first conductivity type formed in the first well;

a gated diode having a layer of first material formed on the second well and a diode gate formed on the layer of first material;

a first transistor formed in the second well, the first transistor being spaced apart from the gated diode, the first transistor having a source region and a drain region formed in the second well, the source region being spaced apart from the drain region; and

a cell diode connected between the gated diode and ground.

21. The device of claim 20 and further comprising:

an oscillator connected to the gated diode;

a counter connected to the gated diode; and

a controller connected to the oscillator, the counter, and the first transistor.

22. The device of claim 21

wherein the gated diode further has:

a diffusion region of the second conductivity type formed in the second well, the diffusion region being spaced apart from the source region and the drain region; and

an inversion region defined in the second well below the layer of first material, the inversion region adjoining the diffusion region; and

wherein the cell diode is connected between the diffusion region and ground.

23. The device of claim 21 wherein the oscillator is connected to the diode gate.

24. The device of claim 23 wherein the counter is connected to the diode gate.

25. The device of claim 21 wherein the counter is connected to the diode gate.

26. The device of claim 21 wherein the oscillator outputs a series of pulses when commanded by the controller, and stops outputting the pulses when commanded by the controller.

27. The device of claim 26 wherein the counter resets a count when commanded by the controller, counts a number of pulses output by the oscillator, and resets the count when commanded by the controller.

28. The device of claim 21 wherein the counter resets a count when commanded by the controller, counts a number of pulses output by the oscillator, and resets the count when commanded by the controller.

29. The device of claim 21 and further comprising a second transistor connected to the source region and the controller.

30. The device of claim 21 and further comprising:

a variable voltage source; and

a second transistor connected to the second well and the variable voltage source.