Semiconductor device having uniform spacers

• US 6,380,588 B1
• Filed: 05/09/2000
• Issued: 04/30/2002
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yang, Chih-Yuk, Foote, David K., Bell, Scott A., Karlsson, Olov B., Lyons, Christopher F., En, William G., Ngo, Minh Van
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/567,013
• Time in Patent Office: 721 Days
• Field of Search: 257/327, 257/345, 257/900, 438/709, 438/719, 438/695-696, 438/639, 438/595
• US Class Current: 257/345
• CPC Class Codes: H01L 21/31116 by dry-etching

Abstract

A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

Claims

1. A semiconductor device arrangement comprising a semiconductor substrate having a mixture of operational gate arrangements and non-operational gate arrangements on a surface of the substrate, the space between said gate arrangements being substantially the same distance, each operational and non-operational gate arrangement having dielectric spacers which are of uniform shape and size, each spacer having substantially the same width and physically contacting the substrate, wherein removal of the non-operational gate arrangements provides operational gate arrangements on said substrate having uniformly sized spacers and different distances between the operational gate arrangements.

2. The semiconductor device of claim 1, wherein each operational gate arrangement and each non-operational gate arrangement comprises a thin oxide layer formed on the substrate and a polysilicon layer on the thin oxide layer.

3. The semiconductor device of claim 1, wherein the dielectric spacers comprise at least one dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon oxime.