Low dielectric constant etch stop layers in integrated circuit interconnects

• US 6,388,330 B1
• Filed: 02/01/2001
• Issued: 05/14/2002
• Est. Priority Date: 02/01/2001
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Hopper, Dawn M., Huertas, Robert A., Kitson, Terri J.
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US09/776,012
• Time in Patent Office: 467 Days
• Field of Search: 438/622-624, 438/629, 438/631, 438/633, 438/634, 438/637-640, 438/672, 438/675, 438/687, 438/688, 438/692, 438/783, 438/791, 257/758-760, 257/762, 257/765
• US Class Current: 257/760
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.

Claims

1. An integrated circuit comprising:

a semiconductor substrate having a semiconductor device provided thereon;

a first dielectric layer formed over the semiconductor substrate having a first opening provided therein;

a first conductor core filling the first opening and connected to the semiconductor device;

an etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the etch stop layer having a dielectric constant below 5.5;

a second dielectric layer formed over the etch stop layer and having a second opening provided therein open to the first conductor core;

a second conductor core filling the second opening and connected to the first conductor core.

2. The integrated circuit as claimed in claim 1 wherein the etch stop layer is a multilayer structure.

3. The integrated circuit as claimed in claim 1 wherein the etch stop layer is a multilayer structure with each of the layers having a different layer orientation.

4. The integrated circuit as claimed in claim 1 wherein the first and second dielectric layers are of a material having a dielectric constant under 3.9.

5. The integrated circuit as claimed in claim 1 wherein the conductor core contains a material selected from a group consisting of copper, aluminum, gold, silver, a compound thereof, and a combination thereof.

6. An integrated circuit comprising:

a semiconductor substrate having a semiconductor device provided thereon;

a first dielectric layer formed over the semiconductor substrate having a first opening provided therein;

a first conductor core filling the first opening and connected to the semiconductor device;

a via etch stop layer of silicon nitride formed over the first dielectric layer and the first conductor core, the via etch stop layer having a dielectric constant below 5.5;

a via dielectric layer formed over the via etch stop layer and having a via opening provided therein open to the first conductor core;

a channel etch stop layer of silicon nitride formed over the via dielectric layer, the channel etch stop layer having a dielectric constant below 5.5;

a second dielectric layer formed over the via dielectric layer and having a second opening provided therein open to the via opening; and

a second conductor core filling the via and second openings and connected to the first conductor core.

7. The integrated circuit as claimed in claim 6 wherein the via and channel etch stop layers are a multilayer structure.

8. The integrated circuit as claimed in claim 6 wherein the via and channel etch stop layers are multilayer structures with each of the layers having a different layer orientation.

9. The integrated circuit as claimed in claim 6 wherein the first, via, and second dielectric layers are of a material having a dielectric constant under 3.9.

10. The integrated circuit as claimed in claim 6 wherein the first and second conductor cores contain materials selected from a group consisting of copper, gold, silver, a compound thereof, and a combination thereof.