Schmitt trigger with hysteresis and previous-state memory
First Claim
1. An apparatus for generating an output signal based on an input signal, comprising:
- a first detection circuit configured to detect a potential of the input signal and that provides an intermediate output signal having a level based on the potential of the input signal, the first detection circuit having an unaltered threshold potential at which the first detection circuit changes a state of the intermediate output signal, the first detection circuit being coupled to receive an enable signal, the first detection circuit being further configured to be deactivated in response to the enable signal being deasserted;
a second detection circuit coupled to the intermediate output signal and being configured to change a state of the output signal in response to the level of the intermediate output signal changing state; and
a trip-level adjustment circuit coupled to the first detection circuit and configured to influence the first detection circuit such that the intermediate output signal changes state when the input signal is at some potential different from the unaltered threshold potential, the trip-level adjustment circuit comprising a first subcircuit having a first control mechanism coupled to the output signal of the second detection circuit and a first influence control mechanism under control of the input signal;
wherein the first control mechanism is sized sufficiently large in comparison to the first influence control mechanism such that a voltage drop across the first control mechanism is much less than a voltage drop across the first influence control mechanism.
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Accused Products
Abstract
Described is a level-detection circuit having hysteresis and which may be powered down without losing the last state of the circuit. The level-detection circuit includes a first detection circuit, a trip-level adjustment circuit, and a second detection circuit. The first detection circuit may be essentially an inverter, with the output signal of the inverter fed to an input of the second detection circuit. The trip-level adjustment circuit is connected to the output signal and has control connections tied to the input signal. The trip-level adjustment circuit also includes control connections tied to the output signal of the circuit. In short, the trip-level adjustment circuit is configured such that one element of the trip-level adjustment circuit is connected in parallel with one element of the inverter of the first detection circuit when the input signal moves from a one potential to another potential. In addition, the trip-level adjustment circuit may include another element connected in parallel with another element of the inverter of the first detection circuit when the input signal moves in the opposite direction, e.g. from the other potential to the one potential. Moreover, the circuit includes latching circuitry, under control of an enable signal, configured to latch a last state of the trip-level adjustment circuit during a power-down event so that the input signal to the second detection circuit will have the same state when the circuit is powered back up.
37 Citations
21 Claims
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1. An apparatus for generating an output signal based on an input signal, comprising:
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a first detection circuit configured to detect a potential of the input signal and that provides an intermediate output signal having a level based on the potential of the input signal, the first detection circuit having an unaltered threshold potential at which the first detection circuit changes a state of the intermediate output signal, the first detection circuit being coupled to receive an enable signal, the first detection circuit being further configured to be deactivated in response to the enable signal being deasserted;
a second detection circuit coupled to the intermediate output signal and being configured to change a state of the output signal in response to the level of the intermediate output signal changing state; and
a trip-level adjustment circuit coupled to the first detection circuit and configured to influence the first detection circuit such that the intermediate output signal changes state when the input signal is at some potential different from the unaltered threshold potential, the trip-level adjustment circuit comprising a first subcircuit having a first control mechanism coupled to the output signal of the second detection circuit and a first influence control mechanism under control of the input signal;
wherein the first control mechanism is sized sufficiently large in comparison to the first influence control mechanism such that a voltage drop across the first control mechanism is much less than a voltage drop across the first influence control mechanism. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 21)
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10. An apparatus for generating an output signal based on an input signal, comprising:
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a first detection circuit, coupled to receive the input signal, that detects a potential of the input signal and that provides an intermediate output signal having a level based on the potential of the input signal, the first detection circuit having an unaltered threshold potential at which the first detection circuit changes a state of the intermediate output signal, the first detection circuit being coupled to receive an enable signal, the first detection circuit being further configured to be deactivated in response to the enable signal being deasserted;
a second detection circuit coupled to receive the intermediate output signal and being configured to change a state of the output signal in response to the level of the intermediate output signal passing through a second threshold potential;
a trip-level adjustment circuit configured to influence the first detection circuit such that the intermediate output signal passes through the second threshold potential while the input signal is at some potential different from the unaltered threshold potential of the first detection circuit; and
a latching circuit coupled to receive the intermediate output signal and to receive the enable signal, the latching circuit being configured to latch a state of the intermediate output signal in response to the enable signal being deasserted. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
a first latching element under control of the enable signal, coupled to the first subcircuit, and being configured to latch a state of the first subcircuit in response to the enable signal being deasserted; and
a second latching element under control of the enable signal, coupled to the second subcircuit, and being configured to latch a state of the second subcircuit in response to the enable signal being deasserted.
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15. The apparatus of claim 14 wherein the first latching element comprises a transistor, and the second latching element comprises another transistor.
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16. The apparatus of claim 14 wherein the latching circuit further comprises a first latching circuit switch coupled to the first detection circuit and under control of the enable signal, wherein the first latching switch deactivates at least a portion of the first detection circuit in response to the enable signal being deasserted.
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17. The apparatus of claim 16 wherein the latching circuit further comprises a second latching circuit switch coupled to the first detection circuit and under control of the enable signal, wherein the first latching switch deactivates at least another portion of the first detection circuit in response to the enable signal being deasserted.
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18. The apparatus of claim 17 wherein the first detection circuit comprises a first detection transistor connected in series with a second detection transistor, and wherein the first latching circuit switch is coupled to the first detection transistor such that the first latching circuit switch deactivates the first detection transistor when the enable signal is deasserted, and wherein the second latching circuit switch is coupled to the second detection transistor such that the second latching circuit switch deactivates the second detection transistor when the enable signal is deasserted.
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19. The apparatus of claim 18 wherein the first latching circuit switch comprises a transistor, and the second latching circuit switch comprises another transistor.
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20. A method for powering down a circuit that generates an output signal based on an input signal, comprising:
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receiving an input signal at a level-detection circuit;
generating an intermediate output signal by the level-detection circuit based on the input signal;
receiving the input signal at a trip-level adjustment circuit;
influencing the level-detection circuit by the trip-level adjustment circuit such that a level of the intermediate output signal reaches a trip-level of an output inverter when the input signal is at a potential different from an unaltered threshold potential of the level-detection circuit, the influence being based upon a component in the trip-level adjustment circuit in combination with a component in the level-detection circuit;
receiving an enable signal indicating a power-down event, the intermediate output signal having a last state at the occurrence of the power-down event; and
latching the last state of the intermediate output signal such that when a power-up event occurs, the intermediate output signal is at the last state.
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Specification