Method of fabricating micro electro mechanical system structure which can be vacuum-packed at wafer level

• US 6,391,673 B1
• Filed: 11/01/2000
• Issued: 05/21/2002
• Est. Priority Date: 11/04/1999
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ha, Byeoung Ju, Song, Hoon, Baek, Seog-soon, Oh, Yong-soo, Kim, Hyun-cheol
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P
• Application Number:
  US09/702,849
• Time in Patent Office: 566 Days
• Field of Search: 438/64, 438/55, 438/51, 438/106, 438/119, 438/118, 438/125, 438/107, 438/455, 438/446, 438/689, 438/149, 438/105, 251/129.04
• US Class Current: 438/51
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: G01C 19/5769 Manufacturing; Mounting; Housings
• CPC Class Codes: G01P 1/02 Housings
• CPC Class Codes: G01P 15/0802 Details

Abstract

A method of fabricating a micro electromechanical system (MEMS) structure which can be vacuum-packaged at the wafer level is provided. The method includes the steps of forming a multilayered stack including a signal line on a first wafer; bonding a second wafer to the multilayered stack; polishing the first wafer to a predetermined thickness; forming a MEMS structure in a vacuum area of the first wafer and a pad outside the vacuum area, the MEMS structure and the pad being connected to the signal line; forming a structure in a third wafer to have space corresponding to the vacuum area of the MEMS structure; and bonding the third wafer to the polished surface of the first wafer in a vacuum state. For protection of the structure and maintaining a vacuum level required for operation, the fabricated structure is vacuum-packaged at the wafer level, thereby improving the yield of fabrication. In addition, since a special vacuum packaging process is not necessary, the fabrication can be simplified.

Claims

1. A method of fabricating a micro electro mechanical system (MEMS) structure which can be vacuum-packaged at the wafer level, the method comprising the steps of:

i. forming a signal line on a first wafer;

ii. bonding a second wafer to the first wafer to form a multilayered stack;

iii. forming a MEMS structure in a vacuum area of the first wafer in a vacuum state;

iv. forming a structure in a third wafer to have space corresponding to the vacuum area of the MEMS structure; and

v. bonding the third wafer to a surface of the first wafer in a vacuum state.

2. The method of claim 1, wherein the MEMS structure forming step comprises a step of forming a signal line layer for connecting the inner area to the pad.

3. The method of claim 1, wherein the step of bonding the third wafer to the first wafer, includes one of an adhesive or eutectic bonding.

4. The method of claim 1, wherein the step of bonding, the third wafer to the first wafer, includes one of silicon direct bonding or anodic bonding.

5. The method of claim 1, wherein in the step of bonding the third wafer to the first wafer includes eutectic bonding.

6. The method of claim 1, wherein the third wafer is formed of single crystalline silicon.

7. The method of claim 6, wherein the step of forming a structure in the third wafer, includes anisotropic etching.

15. The method of claim 1, further including the step of polishing the first wafer to a predetermined thickness.

8. A method of fabricating a micro electro mechanical system (MEMS) structure which can be vacuum-packaged at the wafer level, the method comprising the steps of:

i. forming a poly silicon layer having a predetermined pattern for a signal line on the sacrificial layer;

ii. forming a poly silicon layer having a predetermined pattern for a signal line on the sacrificial layer;

iii. forming an insulation layer on the poly silicon layer;

iv. bonding a second wafer to the insulation wafer;

v. forming a MEMS structure comprising a resonant plate and a frame supporting the resonant plate in a vacuum area of the first wafer and a pad outside the vacuum area, the MEMS structure and the pad being connected to the signal line;

vi. forming a structure in a third wafer to have space corresponding to the vacuum area of the MEMS structure; and

vii. bonding the third wafer to the polished surface of the first wafer in a vacuum state.

9. The method of claim 8, wherein the step of bonding the third wafer to the first wafer, includes one of an adhesive or eutectic bonding.

10. The method of claim 8, wherein the step of bonding, the third wafer to the first wafer, includes one of silicon direct bonding or anodic bonding.

11. The method of claim 8, wherein the first wafer is formed of single crystalline silicon.

12. The method of claim 11, wherein the step of forming a structure on the third wafer includes anisotropic etching.

13. The method of claim 9, wherein the first wafer is formed of single crystalline silicon.

14. The method of claim 10, wherein the first wafer is formed of single crystalline silicon.

16. The method of claim 8, further including the step of polishing the first wafer to a predetermined thickness.

17. The method of claim 8, wherein the step of bonding the third wafer to the first wafer includes eutectic bonding.