Compound semiconductor device and method of manufacturing the same

• US 6,395,588 B2
• Filed: 06/15/2001
• Issued: 05/28/2002
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: Fujitsu Quantum Devices Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Quantum Devices Limited (Fujitsu Limited)
• Inventors: Kuroda, Shigeru, Igarashi, Tsutomu, Nikaido, Junichiro, Arimochi, Kenji, Mitani, Eizo, Yokoyama, Teruo, Tateno, Yasunori
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/880,867
• Publication Number:
  US 20020008248A1
• Time in Patent Office: 347 Days
• Field of Search: 438/172,167,182,572,573,574,576,579
• US Class Current: 438/172
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜10¹⁶ to 1˜10¹⁷ atoms/cm³, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.

Claims

1. A method of manufacturing a compound semiconductor device comprising the steps of:

forming a channel layer on a semiconductor substrate;

forming a carrier supply layer, which supplies carriers to the channel layer, on the channel layer;

forming a first gallium-arsenide layer on the carrier supply layer;

forming a silicon nitride film on the first gallium-arsenide layer;

heating the first gallium-arsenide layer which is covered with the silicon nitride film;

forming an opening portion by selectively etching the silicon nitride film on a gate region;

forming a gate electrode on the gate region of the carrier supply layer via the opening portion;

forming a source opening portion and a drain opening portion on or above the first gallium-arsenide layer; and

forming a source electrode on or above the first gallium-arsenide layer via the source opening portion and forming a drain electrode on or above the first gallium-arsenide layer via the drain opening portion.

2. A method of manufacturing a compound semiconductor device according to claim 1, further comprising the steps of:

forming a Schottky semiconductor layer between the carrier supply layer and the first gallium-arsenide layer;

forming a second gallium-arsenide layer on the first gallium-arsenide layer;

forming a first recess by etching the second gallium-arsenide layer in the gate region and an environment of the same; and

forming a second recess, which is in the first recess, by etching the first gallium-arsenide layer via the opening portion.

3. A method of manufacturing a compound semiconductor device according to claim 2, further comprising the steps of:

forming an aluminum-arsenide etching stopper layer between the first gallium-arsenide layer and the second gallium-arsenide layer; and

wherein etching of the second gallium-arsenide layer in forming the first recess is stopped at a point of time when the aluminum-gallium-arsenide etching stopper layer is exposed, and

the aluminum-gallium-arsenide etching stopper layer which appears from the first recess is removed after the first recess has been formed.

4. A method of manufacturing a compound semiconductor device according to claim 1, wherein a temperature employed to heat the first gallium-arsenide layer is set in a range of 500 to 700°

C.