Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

• US 6,397,314 B1
• Filed: 11/02/2000
• Issued: 05/28/2002
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US09/705,474
• Time in Patent Office: 572 Days
• Field of Search: 711/103,104,115,168,5,202,102 364/200 360/49,39,54,31 365/185.11,200,210,230.03,189.04
• US Class Current: 711/168
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Claims

1. A memory storage system comprising:

a memory controller coupled to a host for transferring sectors of information; and

one or more nonvolatile memory unit for storing information organized into sectors, each nonvolatile memory unit coupled to said memory controller circuitry via a memory bus, said each nonvolatile memory unit having blocks, each of said blocks including a plurality of sectors, said memory controller receiving more than one sector of information from a host and programming two or more sectors of information to two or more blocks of each non-volatile memory unit simultaneously,

wherein the speed of programming operation is increased by programming two or more sectors to two or more blocks within a nonvolatile memory unit simultaneously.

2. A memory storage system comprising:

memory control circuitry;

a nonvolatile memory unit for storing information organized into sectors, said nonvolatile memory unit coupled to said memory control circuitry via a memory bus, said nonvolatile memory unit including a plurality of rows, each row including a plurality of sector storage locations, each of said sector storage locations providing storage space for at least one of said sectors,

wherein the speed of performing write operations is increased by writing two or more sectors of information to a row of the nonvolatile memory unit simultaneously.

3. A memory storage system as recited in claim 2 wherein said nonvolatile memory unit includes one or more flash memory chips.

4. A memory storage system as recited in claim 3 wherein said rows span across said one or more flash memory chips.

5. A memory storage system as recited in claim 2 wherein each of said sector storage locations includes storage space for 512 bytes of user data.

6. A memory storage system as recited in claim 5 wherein each of said sector storage locations further includes storage space for 16 bytes of overhead information.

7. A memory storage system for storing information organized into sectors within a nonvolatile memory unit, each said sector including a user data portion and an overhead portion, said sectors being organized into blocks, each said sector identified by a host-provided logical block address (LBA) and an actual physical block address (PBA), said host-provided LBA being received by said memory storage system from a host for identifying a sector of information to be accessed, said actual PBA developed by said memory storage system to identify where within said nonvolatile memory unit said one or more sectors received from a host is to be stored, said storage system comprising:

a data buffer for temporarily storing data received from a host;

a control unit for receiving one or more sectors from the host via said data buffer; and

a nonvolatile memory unit having one or more memory locations, each of said memory locations providing storage space for storing two or more sectors,

wherein the speed of performing program operation is increased by programming two or more sectors from a data buffer to a nonvolatile memory device simultaneously.