Pixel cell with high storage capacitance for a CMOS imager

• US 6,407,440 B1
• Filed: 02/25/2000
• Issued: 06/18/2002
• Est. Priority Date: 02/25/2000
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US09/513,470
• Time in Patent Office: 844 Days
• Field of Search: 257/218, 257/222, 257/232, 257/233, 257/234, 257/249, 257/290, 257/291, 257/292, 257/461, 257/462, 257/443, 348/294, 348/308, 377/60
• US Class Current: 257/462
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 μm² to about 10 μm². The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Claims

1. A source follower transistor for use in a CMOS imaging device, said transistor comprising:

a source region formed in a substrate;

a drain region formed in the substrate;

a gate layer formed on the substrate between said source region and said drain region, wherein said gate has an active area of from about 0.3 μ

m² to about 25 μ

m², and wherein said gate layer is adapted to be electrically connected to receive charge from a photocharge collector.

2. The transistor of claim 1, wherein the photocharge collector is a photodiode.

3. The transistor of claim 2, wherein said source and drain regions are doped to a second conductivity type.

4. The transistor of claim 3, wherein the second conductivity type is n-type.

5. The transistor of claim 2, further comprising an insulating layer formed between said gate layer and the substrate.

6. The transistor of claim 5, wherein said insulating layer comprises a layer of silicon dioxide.

7. The transistor of claim 5, wherein said insulating layer comprises a layer of silicon nitride.

8. The transistor of claim 2, wherein said gate layer is a layer of doped polysilicon.

9. The transistor of claim 2, wherein said gate layer is a layer of tungsten.

10. The transistor of claim 2, wherein said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

11. A pixel sensor cell for use in a CMOS imaging device, said cell comprising:

a doped layer formed in a substrate;

a photocharge collector formed on at least a portion of said doped layer for controlling image charge accumulation in said doped layer; and

a source follower transistor having a gate for receiving charge collected by said photocharge collector and for providing a signal representing image charge, wherein the gate of said source follower transistor has an active area of from about 0.3 μ

m² to about 25 μ

m².

12. The pixel sensor cell of claim 11, wherein said photocharge collector is a photodiode.

13. The pixel sensor cell of claim 12, wherein said doped layer is doped to a first conductivity type.

14. The pixel sensor cell of claim 13, wherein the first conductivity type is p-type.

15. The pixel sensor cell of claim 12, wherein said photodiode is a p-n junction photodiode.

16. The pixel sensor cell of claim 12, wherein said photodiode is a PIN photodiode.

17. The pixel sensor cell of claim 12, wherein said photodiode is a Schottky photodiode.

18. The pixel sensor cell of claim 12, further comprising a contact between the gate of said source follower transistor and said photodiode.

19. The pixel sensor cell of claim 18, wherein said contact is formed of doped polysilicon.

20. The pixel sensor cell of claim 18, wherein said contact is formed of tungsten.

21. The pixel sensor cell of claim 18, wherein said contact has a barrier layer formed around an outer surface of said contact.

22. The pixel sensor cell of claim 21, wherein the barrier layer is a layer of titanium.

23. The pixel sensor cell of claim 21, wherein the barrier layer is a layer of titanium nitride.

24. The pixel sensor cell of claim 11, said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

25. The pixel sensor cell of claim 11, wherein the gate of said source follower transistor comprises a layer of doped polysilicon.

26. The pixel sensor cell of claim 11, wherein the gate of said source follower transistor is a layer of tungsten.

27. The pixel sensor cell of claim 11, wherein the gate of said source follower transistor is a layer of tungsten silicide.

28. The pixel sensor cell of claim 11, further comprising a doped region formed in said doped layer adjacent to said photodiode for receiving image charge transferred from said doped layer.

29. The pixel sensor cell of claim 28, wherein said doped region is doped n+.

30. The pixel sensor cell of claim 29, further comprising a transfer gate formed on said doped layer between said photodiode and said doped region for gating image charge accumulated in said doped layer to said doped region.

31. A pixel sensor cell for use in a CMOS imaging device, said cell comprising:

a doped layer formed in a substrate;

a photocharge collector formed on at least a portion of said doped layer for controlling image charge accumulation in said doped layer;

a doped region formed in said doped layer adjacent to said photocharge collector for receiving image charge transferred from said doped layer; and

a source follower transistor having a gate electrically connected to receive charge from said doped region and for providing a signal representing image charge transferred to said doped region, wherein the gate of said source follower transistor has an active area of from about 0.3 μ

m² to about 25 μ

m².

32. The pixel sensor cell of claim 31, said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

33. The pixel sensor cell of claim 31, wherein said photocharge collector is a photodiode.

34. The pixel sensor cell of claim 31, wherein said doped layer is doped to a first conductivity type.

35. The pixel sensor cell of claim 34, wherein the first conductivity type is p-type.

36. The pixel sensor cell of claim 35, wherein the first conductivity type is n-type.

37. The pixel sensor cell of claim 33, wherein said photodiode is a p-n junction photodiode.

38. The pixel sensor cell of claim 33, wherein said photodiode is a PIN photodiode.

39. The pixel sensor cell of claim 33, wherein said photodiode is a Schottky photodiode.

40. The pixel sensor cell of claim 33, wherein said doped region is doped to a second conductivity type.

41. The pixel sensor cell of claim 40, wherein the second conductivity type is n-type.

42. The pixel sensor cell of claim 40, wherein the second conductivity type is p-type.

43. The pixel sensor cell of claim 33, further comprising a contact between the gate of said source follower transistor and the doped region.

44. The pixel sensor cell of claim 43, wherein said contact is formed of doped polysilicon.

45. The pixel sensor cell of claim 43, wherein said contact is formed of tungsten.

46. The pixel sensor cell of claim 43, wherein said contact has a barrier layer formed around an outer surface of said contact.

47. The pixel sensor cell of claim 46, wherein the barrier layer is a layer of titanium.

48. The pixel sensor cell of claim 46, wherein the barrier layer is a layer of titanium nitride.

49. The pixel sensor cell of claim 33, further comprising a transfer gate formed on said doped layer between said photodiode and said doped region for gating image charge accumulated in said doped layer to said doped region.

50. A CMOS imager comprising:

a doped layer formed in a substrate;

an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a photocharge collector and a source follower transistor having a gate, the gate of the source follower transistor receiving charge collected by said photocharge collector and having an active area of from about 0.3 μ

m² to about 25 μ

m²; and

signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image.

51. The CMOS imager of claim 50, said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

52. The CMOS imager of claim 50, wherein the photocharge collector is a photodiode.

53. The CMOS imager of claim 52, wherein said doped layer is doped to a first conductivity type.

54. The CMOS imager of claim 53, wherein the first conductivity type is p-type.

55. The CMOS imager of claim 53, wherein the first conductivity type is n-type.

56. The CMOS imager of claim 53, wherein the doped silicon is doped polysilicon.

57. The CMOS imager of claim 53, wherein the gate is a layer of tungsten.

58. The CMOS imager of claim 53, wherein the gate is a layer of tungsten silicide.

59. The CMOS imager of claim 53, wherein each pixel sensor cell has a doped region formed in said doped layer adjacent to the photodiode for receiving image charge transferred from said doped layer.

60. The CMOS imager of claim 59, wherein the doped region is doped n+.

61. The CMOS imager of claim 60, wherein each pixel sensor cell has a transfer gate formed on said doped layer between the photodiode and the doped region for gating image charge accumulated in said doped layer to the doped region.

62. An array of pixel sensor cells comprising:

a doped layer formed in a substrate;

a plurality of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a source follower transistor having a gate having an active area of from about 0.3 μ

m² to about 25 μ

m².

63. The array of claim 62, said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

64. The array of claim 62, wherein said doped layer is doped to a first conductivity type.

65. The array of claim 62, wherein the gate is a formed of doped polysilicon.

66. The array of claim 62, wherein the gate is a layer of tungsten.

67. The array of claim 62, wherein the gate is a layer of tungsten silicide.

68. An imaging system for generating output signals based on an image focused on the imaging system, comprising:

a plurality of pixel cells arranged into an array of rows and columns, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light intensity by the cell, wherein each pixel cell has a source follower transistor with a gate having an active area of from about 0.3 μ

m² to about 25 μ

m²;

a row decoder having a plurality of control lines connected to the cell array, each control line being connected to the cells in a respective row, wherein the row decoder is operable to activate the cells in a row; and

a plurality of output circuits each including a respective output transistor, each output circuit being connected to a respective cell of said array, each circuit being operable to store voltage signals received from a respective cell and to provide a cell output signal.

69. The imaging system of claim 68, said transistor gate has an area of from about 1.0 μ

m² to about 15 μ

m².

70. The imaging system of claim 68, wherein the gate is a formed of doped polysilicon.

71. The imaging system of claim 68, wherein the gate is a layer of tungsten.

72. The imaging system of claim 68, wherein the gate is a layer of tungsten silicide.

73. An integrated circuit imager comprising:

a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a doped layer on a substrate, wherein each pixel sensor cell has a source follower transistor having an active area of from about 1.0 μ

m² to about 15.0 μ

m², and signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a processor for receiving and processing data representing said image.