Method and apparatus for providing event handling functionality in a computer system

• US 6,408,386 B1
• Filed: 01/25/2001
• Issued: 06/18/2002
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kahn, Kevin, Hammond, Gary, Alpert, Donald, Sharangpani, Harsh
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/770,970
• Time in Patent Office: 509 Days
• Field of Search: 712/244, 712/200, 710/269
• US Class Current: 712/244
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Method And Apparatus for Providing Event Handling Functionality in a Computer System. According to one embodiment of the invention, a computer system includes an instruction set unit and an event handling unit in a processor, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit is to cause the processor to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

Claims

1. A computer system comprising:

an instruction set unit in a processor to support a first and second instruction sets, problems arising during processing of instructions from said first and second instruction sets respectively causes a first and second set of events;

a first plurality of event handlers including a first event handler; and

an event handling unit, in said processor, to cause said processor to execute the appropriate one of said first plurality of event handlers, at least some of said first set of events being mapped to different ones of the first plurality of event handlers, all of the second set of events being mapped to said first event handler.

2. The computer system of claim 1, wherein:

said event handling unit, responsive to each of said second set of events, to record which of said second set of events has occurred and to cause the processor to execute said first event handler; and

said first event handler to cause said processor to determine which of said second set of events has occurred based on the record.

3. The computer system of claim 2, further comprising:

a second plurality of event handlers;

an interrupt vector table having entries identifying different ones of said second plurality of event handlers for said second set of events; and

said first event handler, responsive to each of said second set of events, to cause said processor to access said interrupt vector table based on which of said second set of events has occurred and select the identified one of said second plurality of event handlers.

4. The computer system of claim 3, wherein the first plurality of event handlers are written in instructions from the first instruction set, and the second plurality of event handlers is written in instructions from said second instruction set.

5. The computer system of claim 4, wherein said second instruction set is compatible with the x86 instruction set.

6. The computer system of claim 3, wherein the first plurality of event handlers is stored in an event handler region, the event handler region being divided into sections with each of said first plurality of event handlers being stored in a different one of said sections.

7. The computer system of claim 6, wherein said event handler, responsive to the occurrence of one of said events, calculates the address of the appropriate section in the event handler;

region by adding a base address of the event handler region with a predetermined value multiplied by a number assigned to the section assigned to the occurred event.

8. The computer system of claim 2, wherein the first plurality of event handlers is stored in an event handler region, the event handler region being divided into sections with each of said first plurality of event handlers being stored in a different one of said sections.

9. The computer system of claim 2, wherein said event handler, responsive to the occurrence of one of said events, calculates the address of the appropriate section in the event handler region by adding a base address of the event handler region with a predetermined value multiplied by a number assigned to the section assigned to the occurred event.

10. A computer implemented method comprising:

detecting the occurrence of an event, said event arising as a result of processing instructions from either a first or a second instruction set, wherein problems arising during the processing of instructions from said first and second instruction sets respectively causes a first and second set of events;

calculating the address of one of a first plurality of event handlers written to handle said event, wherein at least some of said first set of events are assigned to different ones of said first plurality of event handlers, and all of said second set of events are mapped to a first of said first plurality of event handlers; and

executing the event handler stored at the calculated address.

11. The method of claim 10, wherein:

said detecting includes for each of said second set of events, recording which of said second set of events has occurred; and

said executing includes,

responsive to executing said first event handler, determining which of said

second set of events has occurred based on the record.

12. The method of claim 10, wherein:

said detecting includes for each of said second set of events, recording which of said second set of events has occurred; and

said executing includes,

responsive to executing said first event handler, determining which of said second set of events has occurred based on the record, wherein a interrupt vector table has stored in its entries data identifying different ones of a second plurality event handlers for said second set of events; and

accessing an entry of said interrupt vector table based on which of said second set of events has occurred;

executing the one of said second plurality of event handlers identified by the accessed entry of said interrupt vector table.

13. A computer implemented method comprising:

detecting an event indicating a problem has arisen during the processing of instructions from a first instruction set;

recording which of a first plurality of events has occurred;

calculating the address of a first of a first plurality of event handlers, wherein said first plurality of event handlers are stored in an event handling region, said event handling region being divided into sections with each section storing one of said first plurality of event handlers;

executing the one of said first plurality of event handlers stored at said calculated address, said executing including,

determining which of said first plurality of events has occurred based on said record, wherein each entry of an interrupt vector table is assigned to one of said first plurality of events, said entries having stored therein data identifying different ones of a second plurality of event handlers; and

accessing the entry of the interrupt vector table for the detected event; and

executing the one of said second plurality of event handlers identified by the accessed entry in the interrupt vector table.

14. The method of claim 13, wherein the first instruction set is compatible with the x86 instruction set.

15. The method of claim 13, wherein the detecting includes the event indicating the problem has arisen during the processing of instructions from a second instruction set.