Method for producing an EEPROM memory cell with a trench capacitor

• US 6,410,391 B1
• Filed: 06/30/2000
• Issued: 06/25/2002
• Est. Priority Date: 07/02/1999
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Zelsacher, Rudolf
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/607,317
• Time in Patent Office: 725 Days
• Field of Search: 438/241, 438/242, 438/249, 438/257, 438/259, 438/264, 438/246, 438/247, 438/586
• US Class Current: 438/259
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention provides a method for fabricating an EEPROM memory cell having a trench capacitor, having the following steps: formation of a trench (108) in a substrate (101); formation of a buried plate (165) in the substrate region in the vicinity of the lower region of the trench (108); concerted fabrication of a floating gate surrounded by dielectric layers in order to define the EEPROM region; optional recessing of the dielectric layer in order to define DRAM regions.

Claims

1. A method for fabricating an EEPROM memory cell having a trench capacitor, which comprises:

providing a substrate having a weakly doped epitaxial layer and a more heavily doped layer disposed under the weakly doped epitaxial layer;

forming a trench in the substrate, the trench having a lower region and an upper region, the lower region at least partially in the weakly doped epitaxial layer;

filling the lower region of the trench with a first filling material;

forming an insulation collar in the upper region of the trench;

removing the first filling material from the lower region of the trench;

forming a buried plate as a first capacitor plate in the lower region of the trench in the weakly doped epitaxial layer;

filling the trench with a conductive second filling material to form a second capacitor plate;

providing a capacitor dielectric between the conductive second filling material and the buried plate;

forming a dielectric tunnel layer in the trench at an interface of a buried contact and an associated selection transistor; and

forming a conductive protective layer on the dielectric tunnel layer.

2. The method according to claim 1, wherein the dielectric tunnel layer is at least one of an oxide layer, a nitride layer, and an oxynitride layer.

3. The method according to claim 1, wherein the substrate is a heavily p-doped semiconductor material having a buried well with n-type doping and a region with weak p-doping disposed above the buried well, the region with weak p-doping having formed therein the buried contact with the associated selection transistor.

4. The method according to claim 1, which further comprises:

removing the conductive second filling material and the insulation collar in the upper region of the trench to uncover the buried contact with the associated selection transistor;

carrying out the tunnel layer forming step by applying the dielectric tunnel layer on the interface of the buried contact and the conductive second filling material;

carrying out the protective layer forming step by applying the conductive protective layer on the tunnel layer; and

anisotropically etching the conductive protective layer and the tunnel layer resulting in the removal of the protective layer and the tunnel layer from the conductive second filling material, with the protective layer and the tunnel layer remaining in a region of the interface of the buried contact and the conductive second filling material.

5. The method according to claim 3, which further comprises:

removing the conductive second filling material and the insulation collar in the upper region of the trench to uncover the buried contact with the associated selection transistor;

carrying out the tunnel layer forming step by applying the dielectric tunnel layer on the interface of the buried contact and the conductive second filling material;

carrying out the protective layer forming step by applying the conductive protective layer on the tunnel layer; and

anisotropically etching the conductive protective layer and the tunnel layer resulting in the removal of the protective layer and the tunnel layer from the conductive second filling material with the protective layer and the tunnel layer remaining in a region of the interface of the buried contact and the conductive second filling material.

6. The method according to claim 4, which further comprises:

after the anisotropic etching, forming a strap above the insulation collar and on the conductive second filling material to the protective layer, the strap being made from a conductive third filling material;

planarizing and sinking the strap; and

forming an STI trench in the upper portion of the trench for insulating the EEPROM cell from other cells in an EEPROM matrix and for preventing strap formation between adjacent capacitors.

7. The method according to claim 5, which further comprises:

after the anisotropic etching, forming a strap above the insulation collar and on the conductive second filling material to the protective layer, the strap being made from a conductive third filling material;

planarizing and sinking the strap; and

forming an STI trench in the upper portion of the trench for insulating the EEPROM cell from other cells in an EEPROM matrix and for preventing strap formation between adjacent capacitors.

8. The method according to claim 6, wherein the second and third conductive filling material is polysilicon.

9. The method according to claim 7, wherein the second and third conductive filling material is polysilicon.

10. The method according to claim 6, which further comprises recessing the dielectric tunnel layer to define DRAM regions.