Method and apparatus for addressing multiple frame buffers

• US 6,411,302 B1
• Filed: 01/06/1999
• Issued: 06/25/2002
• Est. Priority Date: 01/06/1999
• Status: Expired due to Fees

• Current Assignee: Robert Carmine Chiraz
• Original Assignee: Concise Multimedia And Communications Inc.
• Inventors: Chiraz, Robert Carmine
• Primary Examiner(s): Zimmerman, Mark
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/226,350
• Time in Patent Office: 1,266 Days
• Field of Search: 345/516, 345/515, 345/511, 345/507, 345/555, 345/540, 345/545, 345/541, 345/542, 345/543, 345/544, 345/531, 345/537, 348/552, 348/446
• US Class Current: 345/545
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G06F 3/153 using cathode-ray tubes
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2340/04 Changes in size, position or resolution of an image
• CPC Class Codes: G09G 2360/04 Display device controller operating with a plurality of display units
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple frame buffers as a single logical frame buffer is made possible by first dividing the image data into pages using a page size appropriate for both the video mode and arrangement of the physical frame buffers within the high resolution image. Then a pitch is determined for each of the physical frame buffers that enables the alignment of the memory pages at the frame buffer crossovers. Then for video modes utilizing multiple bytes per pixel, the collection of bytes representing the pixels are aligned on the page boundaries at the frame buffer crossovers. Then linear address space is reserved for storing a single high resolution frame buffer. Then address translation hardware is configured to shuffle the mapping of the pages such that the pages within the reserved linear address space are routed to the appropriate pages within the multiple physical frame buffers to create a single high resolution frame buffer when accessed with an appropriate logical pitch.

Claims

1. A method of addressing a plurality of video memory areas having a predetermined arrangement, as a logical frame buffer comprising the steps of:

(a) providing a display controller subsystem means which couples a video memory subsystem means to a video device subsystem means via a plurality of video streams;

(b) providing an address translation means which accepts a logical address as an input and responsively generates a translated output for accessing said video memory subsystem means;

(c) locating each of the video memory areas within said video memory subsystem means;

(d) configuring a physical pitch for each of the video memory areas such that said physical pitch corresponds to the difference in video memory addresses between adjacent vertical pixels in the video memory area;

(e) reserving a number of logical address space pages for said logical frame buffer sufficient in size for storing said predetermined arrangement of the video memory areas; and

(f) configuring said address translation means to map the reserved logical address space pages to pages within the video memory areas such that any adjacent vertical pixels in said predetermined arrangement of video memory areas are separated by a constant number of logical addresses, said constant corresponding to a logical pitch for accessing said logical frame buffer, wherein;

each of the video memory areas is coupled to one or more video streams,

two or more of the video streams are coupled to distinct video memory areas and have a common video direction;

said display controller subsystem means contains one or more display controllers; and

adjacent vertical pixels correspond to pixels in distinct scan lines.

2. The method of claim 1 wherein step (f) comprises initializing said address translation means to configure the mapping of the reserved logical address space pages, wherein the initialization is accomplished by writing values into a look up table means.

3. The method of claim 1, further comprising the step of initializing a set of parameters that define a primary display surface, said set of parameters corresponding to said logical frame buffer, wherein said primary display surface is accessed by an operating system software component when processing graphics commands.

4. The method of claim 3, further comprising the step of providing one or more software modules that each process a graphics command, wherein each software module configures graphics acceleration hardware to access one or more of the video memory areas.

5. The method of claim 1 wherein step (c) comprises determining a start address offset for each of one or more of the video memory areas such that the video memory area is page aligned in video memory at a boundary between adjacent video memory areas in said predetermined arrangement.

6. The method of claim 1 wherein step (d) is performed simultaneously with step (c) and wherein step (d) comprises determining said physical pitch for each of one or more of the video memory areas such that the video memory area is page aligned in video memory at one or more boundaries between adjacent video memory areas in said predetermined arrangement.

7. The method of claim 1, further comprising the step of converting a X coordinate to a Y coordinate and converting a Y coordinate to a X coordinate prior to forming a logical address for accessing said logical frame buffer, wherein the unconverted X and Y coordinates correspond to a rotated logical frame buffer.

8. The method of claim 1, further comprising the step of providing a panning means for positioning a sub-area within any of the video memory areas, wherein any of the video streams coupled to the video memory area transports image data associated with said sub-area.

9. The method of claim 1 wherein step (c) further comprises reserving video memory adjacent to any of the video memory areas, wherein the reserved video memory is used for storing image data corresponding to test patterns during a display calibration procedure.

10. The method of claim 1, further comprising the step of determining a page size responsive to said predetermined arrangement of the video memory areas and responsive to the page size limitations of said address translation means.

11. The method of claim 1, further comprising the step of configuring said display controller subsystem means to perform scaling such that the number of pixels that are logically addressable within any of said video memory areas differs from the number of pixels that are coupled via the associated video streams to said video device subsystem means.

12. The method of claim 1 wherein said logical frame buffer stores data representing color information.

13. The method of claim 1 wherein said logical frame buffer stores data representing alpha values.

14. The method of claim 1 wherein said logical frame buffer stores data representing z-buffer values.

15. A computer system for addressing a plurality of video memory areas having a predetermined arrangement, as a logical frame buffer comprising:

(a) a video memory subsystem means which contains the video memory areas;

(b) a display controller subsystem means which couples said video memory subsystem means to a video device subsystem means via a plurality of video streams; and

(c) an address translation means which will;

(1) separate a logical address space into logical address space pages;

(2) accept a logical address as an input and responsively generate a translated output for accessing said video memory subsystem means;

(3) map logical address space pages to pages within the video memory areas such that any adjacent vertical pixels in said predetermined arrangement of video memory areas are separated by a constant number of logical addresses, said constant corresponding to a logical pitch for accessing said logical frame buffer;

wherein each of the video memory areas is coupled to one or more video streams;

wherein two or more of the video streams are coupled to distinct video memory areas and have a common video direction;

wherein said display controller subsystem means contains one or more display controllers; and

wherein adjacent vertical pixels correspond to pixels in distinct scan lines.

16. The computer system of claim 15 wherein said common video direction is video output.

17. The computer system of claim 16 wherein one or more of said video streams are coupled to one or more video memory areas and have a video input direction.

18. The computer system of claim 15 wherein said common video direction is video input.

19. The computer system of claim 15 wherein any of the distinct video memory areas is coupled to two or more video streams of said common video direction.

20. The computer system of claim 19 wherein said common video direction is video output.

21. The computer system of claim 15 wherein said address translation means is comprised of a look up table means.

22. The computer system of claim 21 wherein said look up table means consists of a processor'"'"'s page translation means.

23. The computer system of claim 21 wherein said look up table means includes a processor'"'"'s page translation means.

24. The computer system of claim 21 wherein said look up table means includes a non-volatile memory means.

25. The computer system of claim 21 wherein said look up table means includes a circuit for rerouting address lines, wherein the width of any of the video memory areas is a power of two.

26. The computer system of claim 21 wherein said look up table means includes circuitry integrated with a display controller means.

27. The computer system of claim 26, further comprising a disconnect means to terminate burst accesses at boundaries between adjacent video memory areas.

28. The computer system of claim 21 wherein said look up table means includes circuitry integrated with a bus interface means.

29. The computer system of claim 28, further comprising a disconnect means to terminate burst accesses at boundaries between adjacent video memory areas.

30. The computer system of claim 15 wherein said translated output is comprised of an output address.

31. The computer system of claim 15 wherein said translated output is comprised of an output address and a plurality of video memory enable means'"'"'s.

32. The computer system of claim 31 wherein the video memory enable means'"'"'s includes bus cycle framing signal means'"'"'s.

33. A method of re-allocating memory for a display surface in a display device driver software component when said display surface is positioned such that it spans a plurality of video memory areas comprising the steps of:

(a) providing a display controller subsystem means which couples the video memory areas to a video device subsystem means via a plurality of video streams;

(b) providing an address translation means which accepts logical addresses as an input and responsively generates a translated output for accessing the video memory areas;

(c) responding to a software application'"'"'s request for said display surface to be created by allocating memory for the surface in an initial surface memory means which is accessible by the software application;

(d) responding to a software application'"'"'s request for said display surface to be positioned by allocating a logical frame buffer to address the video memory areas;

(e) transferring data from said initial surface memory means to the video memory areas; and

(f) modifying a start address value and a pitch value that are associated with said display surface to values that correspond to said logical frame buffer.