Leaky lower interface for reduction of floating body effect in SOI devices

• US 6,417,030 B1
• Filed: 02/20/2001
• Issued: 07/09/2002
• Est. Priority Date: 01/18/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Buynoski, Matthew S., Wollesen, Donald L.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V
• Application Number:
  US09/789,134
• Time in Patent Office: 504 Days
• Field of Search: 438/149, 438/164, 438/295, 438/412, 438/406, 438/459, 438/524, 438/977, 438/FOR.222, 148/DIG.12
• US Class Current: 438/149
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a first wafer having a first semiconductor substrate, a first insulating layer on the semiconductor substrate, and an altered interface region along an interface between the semiconductor substrate and the insulating layer;

bonding the first wafer to a second wafer having a second substrate and a second insulating layer on the substrate, the first and second insulating layers being bonded together;

removing a portion of the first semiconductor substrate to leave a semiconductor thin film on the first insulating layer; and

forming a body region of a first conductivity type and a source region of a second conductivity type in the thin film, the body region and the source region being electrically connected by the altered interface region.

2. The method of claim 1, wherein the forming a first wafer also includes etching the first semiconductor substrate to provide a guide for location of the body region and the source region.

3. The method of claim 2, wherein the etching includes forming an etching mask on the first semiconductor substrate and removing the etching mask prior to depositing the first insulating layer on the first semiconductor substrate, and wherein the forming a first wafer further includes implanting a semiconductor implant material in the first semiconductor material to form the altered interface region, the implanting utilizing the mask to control the location of the implant.

4. The method,of claim 1, wherein the forming a first wafer includes implanting a semiconductor implant material in the first semiconductor substrate to form the altered interface region.

5. The method of claim 4, wherein the semiconductor implant material is selected from a group consisting of germanium, xenon, antimony, and indium.

6. The method of claim 4, wherein the implanting includes a selective implanting through unmasked portions of a surface of the first semiconductor substrate.

7. The method of claim 4, wherein the implanting includes a maskless implanting.

8. The method of claim 1, wherein the forming a first wafer includes implanting an implant material into the first insulating layer to form the altered interface region.

9. The method of claim 8, wherein the insulation implant material is selected from a group consisting of iron, nickel, vanadium, and titanium.

10. The method of claim 8, wherein the implanting includes a selective implanting through unmasked portions of a surface of the first insulating layer.

11. The method of claim 8, wherein the implanting includes a maskless implanting.

12. The method of claim 1, wherein the semiconductor thin film includes a bottom portion in contact with the first insulating layer, and a top portion not in contact with the first insulating layer;

and wherein the altered interface region is substantially wholly within the bottom portion.

13. The method of claim 1, wherein the altered interface region is substantially wholly within the insulating layer.

14. The method of claim 1, wherein the forming the first wafer includes etching a portion of the first semiconductor substrate to form a stepped surface of the first semiconductor substrate.

15. The method of claim 14, wherein the forming the first wafer also includes forming a stepped interface region at the interface between the semiconductor substrate and the Insulating layer, along the stepped surface.

16. The method of claim 15, wherein the forming the first wafer includes forming the altered interface region along the stepped interface region.

17. The method of claim 15, wherein the forming the body region and the source region includes using the stepped interface region as a guide in forming the body region and the source region.

18. A method of fabricating a semiconductor device, comprising:

forming an altered interface region at an interface between a semiconductor material and an insulating layer removing a portion of the semiconductor material to leave a remaining semiconductor material film; and

thereafter forming a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor material film, the body region and the source region being electrically connected by the altered interface region.

19. The method of claim 18, wherein the forming the altered interface region includes implanting a semiconductor implant material in the semiconductor material to form the altered interface region.

20. The method of claim 19, wherein the implanting includes a selective implanting through unmasked portions of a surface of the first semiconductor substrate.

21. The method of claim 18, wherein the forming a first wafer includes implanting an implant material into the first insulating layer to form the altered interface region.

22. The method of claim 21, wherein the implanting includes a selective implanting through unmasked portions of a surface of the first insulating layer.

23. The method of claim 21, wherein the implanting includes a maskless implanting.

24. The method of claim 18, wherein the semiconductor material includes a bottom portion in contact with the insulating layer, and a top portion not in contact with the insulating layer;

and wherein the altered interface region is substantially wholly within the bottom portion of the semiconductor material.

25. The method of claim 18, herein the altered interface region is substantially wholly within the insulating layer.

26. The method of claim 18, further comprising, after the forming the altered interface region and prior to the forming the body region and the source region, bonding the insulating layer to another insulator layer of a wafer having a semiconductor substrate.

27. The method of claim 18, further comprising forming a stepped interface region at the interface between the semiconductor material and the insulating layer.

28. The method of claim 27, wherein the forming the stepped interface region includes etching a portion of the semiconductor material to produce a stepped surface.

29. The method of claim 27, wherein the forming the altered Interface region includes forming the altered interface region at the stepped interface region.

30. The method of claim 28, wherein the forming the body region and the source region includes using the stepped interface region as a guide in forming the body region and the source region.