Matrix-addressable display with minimum column-row overlap and maximum metal line-width

• US 6,417,627 B1
• Filed: 02/03/1999
• Issued: 07/09/2002
• Est. Priority Date: 02/03/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derraa, Ammar
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Alemu, Ephrem
• Application Number:
  US09/243,929
• Time in Patent Office: 1,252 Days
• Field of Search: 315/169.3, 315/169.1, 315/169.4, 313/293, 313/310, 313/500, 445/24, 345/76, 345/74, 345/75.2
• US Class Current: 315/169.3
• CPC Class Codes: H01J 31/127 using large area or array sources, i.e. essentially a source for each pixel group

Abstract

A matrix-addressable device includes a number of metal column lines having a number of windows underlying locations of intersection where a number of metal row lines overlap or cross the column lines. Each of the windows has a length that is greater than the nominal width of the row line crossing the column line. A layer of a doped semiconductor overlaps each of the windows to electrically couple a number of emitters formed on the doped semiconductor to the column lines. Each of the metal row lines may include a number of windows positioned at the locations where the row and column lines overlap. Each of the windows has a length greater than a nominal width of the column line that the window overlays. A doped semiconductor layer covers each of the windows and is electrically coupled thereto. A number of apertures formed in the doped semiconductor layer aligned with the emitters to form an extraction grid. A layer of dielectric material may separate the column lines from the row lines.

Claims

1. A circuit structure for driving a matrix addressable device, comprising:

a row line having a nominal row width perpendicular to a longitudinal dimension of the row line and having a row input to receive a row driving signal;

a column line having a nominal column width perpendicular to a longitudinal dimension of the column line and having a column input to receive a column driving signal, the column line crossing the row line at a crossing location; and

at least one of the row line and the column line having at least one window formed therein, the window having a window length in a dimension perpendicular to the width of the line in which the window is formed, the window length being greater than the nominal width of the line which it crosses such that the window overlaps the line that it crosses.

2. The circuit structure of claim 1 wherein the matrix addressable device is a field emission device, the column line is electrically coupled to an emitter and the row line is electrically coupled to an extraction grid having a gate proximate the emitter.

3. The circuit structure of claim 1 wherein each of the row line and column line have at least one window formed therein.

4. The circuit structure of claim 1 wherein the matrix addressable device is a matrix addressable display.

5. The circuit structure of claim 1 further comprising:

a dielectric separating at least a portion of the row line from the column line.

6. The circuit structure of claim 1 wherein each of the row line and column line have a window formed at the crossing location, the windows of the row line and column line overlapping at four junctions.

7. The circuit structure of claim 1 wherein the row line has at least one window formed therein.

8. The circuit structure of claim 7, further comprising:

a conductive silicon layer covering at least a portion of the window in the row line and electrically coupled to the row line.

9. The circuit structure of claim 7, further comprising:

a conductive silicon layer filing in at least a portion of the window in the row line and electrically coupled to the row line.

10. The circuit structure of claim 1 wherein the column line has at least one window formed therein.

11. The circuit structure of claim 10, further comprising:

a conductive silicon layer overlaying at least a portion of the window in the column line and electrically coupled to the column line.

12. The circuit structure of claim 10, further comprising:

a conductive silicon layer filing in at least a portion of the window in the column line and electrically coupled to the column line.

13. A circuit structure for driving a matrix addressable device, comprising:

a row line having a nominal width;

a column line having a nominal width, the column line overlapping the row line;

an area of overlap of the column line and the row line; and

at least one of the column line and the row line having an opening formed therein, the opening having an opening length in a dimension perpendicular to the nominal width of the line in which the opening is formed, the opening length being greater than the nominal width of the line which it crosses such that the opening overlaps the line that it crosses.

14. The circuit structure of claim 13 wherein the row line has an opening formed therein at the area of overlap.

15. The circuit structure of claim 14, further comprising:

a semiconductive layer covering at least a portion of the opening in the row line and electrically coupled to the row line.

16. The circuit structure of claim 13 wherein the column line has an opening formed therein at the area of overlap.

17. The circuit structure of claim 16, further comprising:

a semiconductive layer covering at least a portion of the opening in the column line and electrically coupled to the column line.

18. The circuit structure of claim 16 wherein both the row line and the column line have an opening formed therein at the area of overlap.

19. A circuit structure for driving a field emission device, comprising:

a plurality of row lines;

a plurality of column lines spaced from and crossing the row lines at intersection points, each of the column lines having a number of windows formed therein, the windows being spaced along the column line such that the row lines are aligned with respective ones of the windows in the column lines, a length of the windows in the column lines being greater than a width of the row lines such that the windows in column lines overlap the row lines at the points of intersection;

a number of emitters coupled to each of the column lines; and

a number of extraction grids, each of the extraction grids being coupled to one of the row lines and being positioned proximate respective ones of the emitters.

20. The circuit structure of claim 19, further comprising:

a number of emitter pads, each of the emitter pads disposed across a respective window in the column lines and supporting at least one of the emitters to electrically couple the emitter to the column line.

21. The circuit structure of claim 20 wherein the extraction grids comprise a number of apertures formed in the row line and aligned with the respective ones of the emitters.

22. The circuit structure of claim 20 wherein the column lines are metal.

23. The circuit structure of claim 22 wherein the emitter pads are pads of a semiconductor.

24. The circuit structure of claim 19 wherein each of the row lines has a number of windows formed therein, the windows being spaced along the row line and aligned with the windows in the column line.

25. The circuit structure of claim 24 wherein a length of the windows in the row line is greater than a width of the column lines such that the windows in row lines overlap the column lines at the intersection points.

26. The circuit structure of claim 24 wherein the extraction grids comprise:

a number of extraction strips, each of the extraction strips disposed across a respective window in the row lines to electrically couple the extraction strip to the respective row line and having at least one aperture formed therethrough proximate a respective one of the emitters.

27. The circuit structure of claim 26 wherein the extraction strips are strips of a semiconductor.

28. The circuit structure of claim 26, further comprising:

a dielectric material separating the column lines and the emitter pads from the row lines and the extraction strips.

29. A field emission display, comprising:

a plurality of row lines, each of the row lines having a number of windows formed therein, the windows being spaced along the row line;

a plurality of column lines spaced from and crossing the row lines such that the column lines are aligned with respective ones of the windows in the row lines, a length of the windows in the row line being greater than a width of the column lines such that the windows in row lines overlap the column lines;

a number of emitters coupled to each of the column lines;

a number of extraction grids, each of the extraction grids being coupled to one of the row lines and being positioned proximate respective ones of the emitters;

an anode positioned opposite the emitters; and

a cathodoluminescent layer coating a surface of the anode facing the emitters.

30. The circuit structure of claim 29, further comprising:

a number of emitter pads, each of the emitter pads disposed across a respective window in the column lines and supporting at least one of the emitters to electrically couple the emitter to the column line.

31. The circuit structure of claim 29 wherein each of the column lines has a number of windows formed therein, the windows being spaced along the column line and aligned with the windows in the row line.

32. The circuit structure of claim 31, further comprising:

a number of emitter pads, each of the emitter pads disposed across a respective window in the column lines and supporting at least one of the emitters to electrically couple the emitter to the column line.

33. The circuit structure of claim 31 wherein a length of the windows in the column line is greater than a width of the row lines such that the windows in column lines overlap the row lines.

34. The circuit structure of claim 33, further comprising:

a number of emitter pads, each of the emitter pads disposed across a respective window in the column lines and supporting at least one of the emitters to electrically couple the emitter to the column line.

35. A method of forming a drive circuit for an addressable matrix device, comprising:

forming a row line on a substrate;

forming a column line spaced from the row line and crossing the row line at an intersection point;

forming windows in the row line, the windows having a length greater than a width of the column line such that the windows in the row line overlap the column line at the intersection point; and

locating a dielectric between at least a portion of the row line and a portion of the column line.

36. The method of claim 35, further comprising:

forming a semiconductor layer covering at least a portion of the windows in the row line, the semiconductor layer electrically coupled to the row line.

37. The method of claim 35 wherein the step of forming the column line comprises:

forming a column line having a plurality of windows from a conductive material, the windows in the column line aligned with the windows on the row lines.

38. The method of claim 37, further comprising:

positioning a respective one of a number of memory elements proximate each set of aligned windows;

electrically coupling a first terminal of the memory element to the row line; and

electrically coupling a second terminal of the memory element to the column line.

39. The method of claim 35, further comprising:

forming a semiconductor layer covering at least a portion of the windows in the row line, the semiconductor layer electrically coupled to the row line; and

electrically coupling a number of emitters to the row line through the semiconductor layer.

40. The method of claim 39 wherein the step of forming the column line comprises:

forming a column line having a plurality of windows from a conductive material; and

forming a semiconductor layer covering at least a portion of the windows in the column line and electrically coupled to the column line, the semiconductive layer having a plurality of apertures, the apertures aligned with respective ones of the emitters.

41. A method of forming a drive circuit for an addressable matrix display, comprising:

providing a substrate;

forming a number of conductive column lines on the substrate, the column lines each having a number of windows spaced therealong;

forming a number of semiconductor emitter pads at least partially covering each of the windows in the column lines;

forming a number of emitters on the emitter pads;

forming a number of semiconductor extraction grids proximate the emitters;

forming a number of conductive row lines spaced from and crossing the column lines at crossing points, each of the row lines electrically coupled to a respective one of the extraction grids and aligned with windows of the column lines, the row lines having widths less than lenghts of the windows such that the windows overlap the row lines at the crossing points; and

forming a dielectric layer separating the column lines and emitters from the row lines and extraction grids.

42. The method of claim 41 wherein forming a number of conductive column lines on the substrate comprises

depositing a column metal layer on the substrate; and

patterning the column metal layer to form the column lines and the windows, the windows having a length greater than a width of the row lines.

43. The method of claim 41 wherein forming a number of conductive column lines on the substrate comprises

depositing a column metal layer on the substrate;

and

patterning the column metal layer to form the column lines and the windows.

44. The method of claim 43 wherein forming a number of semiconductor emitter pads comprises:

depositing a first semiconductor layer having a first doping over the column lines and substrate; and

etching the first semiconductor layer to form the emitter pads.

45. The method of claim 44 wherein forming a number of emitters on the emitter pads comprises:

depositing a second semiconductor layer having a second doping over the first semiconductor layer; and

etching the second semiconductor layer to form the emitters.

46. The method of claim 45 wherein etching the first semiconductor layer to form the emitter pads follows etching the second semiconductor layer to form the emitters.

47. The method of claim 45 wherein forming a number of semiconductor extraction grids comprises:

depositing a third semiconductor layer over the dielectric layer; and

planerizing the third semiconductor layer to form a number of apertures aligned with and exposing the emitters.

48. The method of claim 47 wherein forming a number of semiconductor extraction grids further comprises:

patterning the third semiconductor layer to electrically isolate each extraction grid.

49. The method of claim 47 wherein forming a number of conductive row lines comprises:

depositing a row metal layer; and

patterning the row metal layer to form the row lines.

50. The method of claim 47 wherein forming a number of conductive row lines comprises:

depositing a row metal layer; and

patterning the row metal layer to form the row lines, each of the row lines having a number of windows spaced therealong, the windows of the row lines spaced to align with the windows of the column lines.

51. The method of claim 50 and further comprising:

patterning the third semiconductor layer to electrically isolate each extraction grid after patterning the row metal layer to form the row lines.

52. The method of claim 47 wherein forming a number of conductive row lines comprises:

depositing a row metal layer; and

patterning the row metal layer to form the row lines, each of the row lines having a number of windows spaced therealong, the windows of the row lines having a length greater than a width of the column lines and being spaced to align with the windows of the column lines such that the windows of the row lines overlap the windows of the column lines at four junctions at the crossing points.