Method and apparatus for identifying a waveform period

• US 6,417,701 B1
• Filed: 09/29/2000
• Issued: 07/09/2002
• Est. Priority Date: 09/29/2000
• Status: Expired due to Term

• Current Assignee: Rockwell Technologies, LLC
• Original Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Inventors: Bolda, Daniel J.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/675,243
• Time in Patent Office: 648 Days
• Field of Search: 327/39, 327/40, 327/41, 327/44, 327/46, 327/47, 327/78-80, 327/122, 327/125, 327/133-135, 327/333, 327/347, 327/349
• US Class Current: 327/79
• CPC Class Codes: H03K 5/088 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13

Abstract

A technique is provided for identifying waveform period or specific events during a waveform period. A periodic waveform is an input signal for a comparator, voltage divider and a balanced load. The circuitry produces a square waveform that has the same period as the input waveform, but is phase shifted based upon time required for the input waveform to cross positive and negative offsets from a zero axis. The resulting timing signals may be used for analysis of the input waveform, such as for RMS calculations based upon sampling of the input waveform.

Claims

1. A circuit for identifying the period of a waveform, comprising:

a comparator comprising a first input, a second input and an output;

a balanced load circuit coupled to the output of the comparator and configured to provide feedback to the second input of the comparator; and

a level shifted driver circuit coupled to the balance load circuit, the driver circuit comprising a driver transistor which is configured to convert the output of the balanced load to a positive logic signal, the level shifted driver circuit being configured to provide the logic signal with a desired offset, the offset corresponding to a waveform received at the second input of the comparator.

2. The circuit set forth in claim 1, wherein the circuit further comprises:

a filter coupled to the first input of the comparator; and

a voltage divider positioned between the balanced load and the second input of the comparator.

3. The circuit set forth in claim 1, wherein the first input of the comparator is configured to receive a periodic waveform.

4. The circuit set forth in claim 3, wherein the second input of the comparator is configured to receive a square waveform.

5. The circuit set forth in claim 4, wherein the output of the comparator is a square waveform comprising transition edges which occur at a desired offset.

6. The circuit set forth in claim 1, wherein the comparator is coupled to a positive voltage source and further coupled to a negative voltage source.

7. The circuit set forth in claim 6, wherein the positive voltage source and the negative voltage source are further coupled to stabilizing capacitors.

8. The circuit set forth in claim 1, wherein the balanced load circuit comprises a plurality of diodes.

9. The circuit set forth in claim 8, wherein the balanced load circuit comprises a high side dual diode, a low side dual diode coupled to the high side dual diode, and a Zener diode coupled to the high side dual diode and further coupled to the low side dual diode.

10. The circuit set forth in claim 1, wherein the balanced load circuit comprises a full wave bridge rectifier comprising a plurality of identically matched diodes.

11. The circuit set forth in claim 1, wherein the level shifted driver circuit is configured to tolerate an emitter-base voltage equal to the absolute value of the voltage across the balance load.

12. The circuit set forth in claim 11, wherein the logic signal is a positive signal and wherein the waveform is a square waveform.

13. The circuit set forth in claim 12, wherein the level shifted driver circuit is coupled to a resistor and further coupled to a positive voltage source.

14. A system for identifying the period of a waveform, comprising:

a sensor;

a control circuit electrically coupled to the sensor and configured to receive sample data from the sensor and calculate a root-mean-square value for a particular waveform; and

a circuit electrically coupled to the control circuit to provide the control circuit with zero-crossing data based upon an offset corresponding to a processed waveform derived from the particular waveform.

15. The system set forth in claim 14, wherein the sensor is configured to monitor current flow through a power conductor and provide a sensor output indication representative of the current flow.

16. The system set forth in claim 15, wherein the current flow is produced by a variable frequency driver.

17. The system set forth in claim 16, further comprising a motor coupled to the variable frequency driver.

18. The system set forth in claim 14, wherein the control circuit produces an output signal which may be used to interrupt the current flow through the power conductor when a power conductor fault condition in detected.

19. The system set forth in claim 18, wherein the power conductor fault condition is one of a ground fault condition, a phase loss condition, and an overcurrent condition.

20. The system set forth in claim 14, wherein the circuit providing the control circuit with zero-crossing data comprises:

a comparator comprising a first input, a second input and an output;

a balanced load circuit coupled to the output of the comparator and configured to provide a hysteretic positive feedback to the second input of the comparator; and

a level shifted driver circuit coupled to the balanced load circuit, the driver circuit comprising a driver transistor which is configured to convert the output of the balanced load to a positive logic signal.

21. The circuit set forth in claim 20, wherein the circuit further comprises:

a filter coupled to the first input of the comparator; and

a voltage divider positioned between the balanced load and the second input of the comparator.

22. The circuit set forth in claim 20, wherein the first input of the comparator is configured to receive a periodic waveform.

23. The circuit set forth in claim 22, wherein the second input of the comparator is configured to receive a square waveform.

24. The circuit set forth in claim 23, wherein the output of the comparator is a square waveform comprising transition edges which occur at a desired offset.

25. The circuit set forth in claim 20, wherein the comparator is coupled to a positive voltage source and further coupled to a negative voltage source.

26. The circuit set forth in claim 25, wherein the positive voltage source and the negative voltage source are further coupled to stabilizing capacitors.

27. The circuit set forth in claim 20, wherein the balanced load circuit comprises a plurality of diodes.

28. The circuit set forth in claim 27, wherein the balanced load circuit comprises a high side dual diode, a low side dual diode coupled to the high side dual diode, and a Zener diode coupled to the high side dual diode and further coupled to the low side dual diode.

29. The circuit set forth in claim 20, wherein the balanced load circuit comprises a full wave bridge rectifier comprising a plurality of identically matched diodes.

30. The circuit set forth in claim 20, wherein the level shifted driver circuit is configured to tolerate an emitter-base voltage equal to the absolute value of the voltage across the balance load.

31. The circuit set forth in claim 30, wherein the level shifted driver circuit is configured to provide a positive logic signal with a desired offset, the offset corresponding to a square waveform received at the second input of the comparator.

32. The circuit set forth in claim 31, wherein the level shifted driver circuit is coupled to a resistor and further coupled to a positive voltage source.

33. A method for determining the period of a waveform, comprising the acts of:

(a) receiving a periodic waveform;

(b) determining when the signal crosses a positive level offset from a zero level for a parameter of the waveform;

(c) determining when the signal crosses a negative level offset from the zero level for the parameter; and

(d) generating an output signal at times corresponding to times at which the signal crossed the positive and negative level offsets.

34. The method set forth in claim 33, wherein the positive level and the negative level offsets are offset an equal amount from the zero level.

35. The method as set forth in claim 33, wherein the output signal is generated only when the signal crosses the positive and negative level offsets for a first time during each period of the waveform.

36. The method as set forth in claim 33, wherein the parameter is voltage.