Hardmask trim process

  • US 6,420,097 B1
  • Filed: 05/02/2000
  • Issued: 07/16/2002
  • Est. Priority Date: 05/02/2000
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of forming circuit structures having linewidths which are smaller than what is achievable by conventional UV lithographic techniques on ultra-thin resist layers, said method comprising the steps of:

  • providing a semiconductor wafer stack formed of a substrate and a device layer above the substrate;

    depositing a hardmask layer over the device layer;

    depositing an ultra-thin resist layer over the hardmask layer;

    forming a resist mask having an initial linewidth;

    anisotropically etching exposed portions of the hardmask layer;

    isotropically etching subsequently the hardmask layer underneath the resist mask to form a hardmask having a final linewidth which is narrower than the initial line width of the resist mask and corresponds to a desired structure linewidth; and

    anisotropically etching the device layer as defined by the hardmask to form a structure having a width substantially equal to the final linewidth of the hardmask.

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